qemu/target
Anton Blanchard e04c5dd139 target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE
A few small optimisations:

In VSX_LOAD_SCALAR_DS() we can don't need to read the VSR via
get_cpu_vsrh().

Split VSX_VECTOR_LOAD_STORE() into two functions. Loads only need to
write the VSRs (set_cpu_vsr*()) and stores only need to read the VSRs
(get_cpu_vsr*())

Thanks to Mark Cave-Ayland for the suggestions.

Signed-off-by: Anton Blanchard <anton@ozlabs.org>
Message-Id: <20190509103545.4a7fa71a@kryten>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29 11:39:45 +10:00
..
alpha target/alpha: Fix user-only floating-point exceptions 2019-05-19 07:30:03 -07:00
arm target/arm: correct return values for WRITE/READ in arm-semi 2019-05-28 10:28:51 +01:00
cris Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
hppa tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
i386 Introduce qemu_guest_getrandom. 2019-05-23 12:57:17 +01:00
lm32 semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00
m68k semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00
microblaze tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
mips Various testing updates 2019-05-28 17:38:32 +01:00
moxie tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
nios2 semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00
openrisc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
ppc target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE 2019-05-29 11:39:45 +10:00
riscv target/riscv: Only flush TLB if SATP.ASID changes 2019-05-24 12:09:25 -07:00
s390x s390x update: 2019-05-21 16:30:13 +01:00
sh4 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
sparc Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
tilegx target/tilegx: Convert to CPUClass::tlb_fill 2019-05-10 11:12:50 -07:00
tricore Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
unicore32 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
xtensa semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00