dff38e7b40
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@688 c046a42c-6fe2-441c-8c8c-71466251a162
434 lines
13 KiB
C
434 lines
13 KiB
C
/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <getopt.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include <sys/mman.h>
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#include <fcntl.h>
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#include <signal.h>
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#include <time.h>
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#include <sys/time.h>
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#include <malloc.h>
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#include <termios.h>
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#include <sys/poll.h>
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#include <errno.h>
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#include <sys/wait.h>
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#include <netinet/in.h>
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#include "cpu.h"
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#include "vl.h"
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//#define DEBUG_CMOS
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#define RTC_SECONDS 0
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#define RTC_SECONDS_ALARM 1
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#define RTC_MINUTES 2
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#define RTC_MINUTES_ALARM 3
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#define RTC_HOURS 4
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#define RTC_HOURS_ALARM 5
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#define RTC_ALARM_DONT_CARE 0xC0
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#define RTC_DAY_OF_WEEK 6
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#define RTC_DAY_OF_MONTH 7
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#define RTC_MONTH 8
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#define RTC_YEAR 9
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#define RTC_REG_A 10
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#define RTC_REG_B 11
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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#define REG_A_UIP 0x80
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#define REG_B_SET 0x80
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#define REG_B_PIE 0x40
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#define REG_B_AIE 0x20
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#define REG_B_UIE 0x10
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struct RTCState {
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uint8_t cmos_data[128];
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uint8_t cmos_index;
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int current_time; /* in seconds */
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int irq;
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uint8_t buf_data[10]; /* buffered data */
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/* periodic timer */
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QEMUTimer *periodic_timer;
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int64_t next_periodic_time;
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/* second update */
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int64_t next_second_time;
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QEMUTimer *second_timer;
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QEMUTimer *second_timer2;
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};
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static void rtc_set_time(RTCState *s);
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static void rtc_set_date_buf(RTCState *s, const struct tm *tm);
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static void rtc_copy_date(RTCState *s);
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static void rtc_timer_update(RTCState *s, int64_t current_time)
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{
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int period_code, period;
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int64_t cur_clock, next_irq_clock;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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if (period_code != 0 &&
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(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
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if (period_code <= 2)
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1);
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
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} else {
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qemu_del_timer(s->periodic_timer);
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}
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}
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static void rtc_periodic_timer(void *opaque)
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{
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RTCState *s = opaque;
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rtc_timer_update(s, s->next_periodic_time);
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s->cmos_data[RTC_REG_C] |= 0xc0;
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pic_set_irq(s->irq, 1);
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}
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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{
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RTCState *s = opaque;
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if ((addr & 1) == 0) {
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s->cmos_index = data & 0x7f;
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} else {
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#ifdef DEBUG_CMOS
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printf("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data);
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#endif
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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/* XXX: not supported */
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s->cmos_data[s->cmos_index] = data;
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data;
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s);
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}
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP);
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rtc_timer_update(s, qemu_get_clock(vm_clock));
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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data &= ~REG_B_UIE;
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s);
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}
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}
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s->cmos_data[RTC_REG_B] = data;
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rtc_timer_update(s, qemu_get_clock(vm_clock));
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data;
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break;
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}
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}
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}
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static inline int to_bcd(RTCState *s, int a)
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{
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if (s->cmos_data[RTC_REG_B] & 0x04) {
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10);
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}
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}
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static inline int from_bcd(RTCState *s, int a)
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{
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if (s->cmos_data[RTC_REG_B] & 0x04) {
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f);
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}
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}
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static void rtc_set_time(RTCState *s)
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{
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struct tm tm1, *tm = &tm1;
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tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
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tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
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tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS]);
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tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
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tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
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tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
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/* update internal state */
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s->buf_data[RTC_SECONDS] = s->cmos_data[RTC_SECONDS];
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s->buf_data[RTC_MINUTES] = s->cmos_data[RTC_MINUTES];
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s->buf_data[RTC_HOURS] = s->cmos_data[RTC_HOURS];
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s->buf_data[RTC_DAY_OF_WEEK] = s->cmos_data[RTC_DAY_OF_WEEK];
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s->buf_data[RTC_DAY_OF_MONTH] = s->cmos_data[RTC_DAY_OF_MONTH];
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s->buf_data[RTC_MONTH] = s->cmos_data[RTC_MONTH];
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s->buf_data[RTC_YEAR] = s->cmos_data[RTC_YEAR];
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s->current_time = mktime(tm);
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}
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static void rtc_update_second(void *opaque)
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{
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RTCState *s = opaque;
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/* if the oscillator is not in normal operation, we do not update */
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if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
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s->next_second_time += ticks_per_sec;
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qemu_mod_timer(s->second_timer, s->next_second_time);
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} else {
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s->current_time++;
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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/* update in progress bit */
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s->cmos_data[RTC_REG_A] |= REG_A_UIP;
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}
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qemu_mod_timer(s->second_timer2,
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s->next_second_time + (ticks_per_sec * 99) / 100);
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}
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}
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static void rtc_update_second2(void *opaque)
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{
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RTCState *s = opaque;
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time_t ti;
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ti = s->current_time;
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rtc_set_date_buf(s, gmtime(&ti));
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_copy_date(s);
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}
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/* check alarm */
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if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
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s->cmos_data[RTC_SECONDS_ALARM] == s->buf_data[RTC_SECONDS]) &&
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((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
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s->cmos_data[RTC_MINUTES_ALARM] == s->buf_data[RTC_MINUTES]) &&
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((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
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s->cmos_data[RTC_HOURS_ALARM] == s->buf_data[RTC_HOURS])) {
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s->cmos_data[RTC_REG_C] |= 0xa0;
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pic_set_irq(s->irq, 1);
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}
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}
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/* update ended interrupt */
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if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
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s->cmos_data[RTC_REG_C] |= 0x90;
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pic_set_irq(s->irq, 1);
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}
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/* clear update in progress bit */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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s->next_second_time += ticks_per_sec;
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qemu_mod_timer(s->second_timer, s->next_second_time);
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}
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static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
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{
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RTCState *s = opaque;
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int ret;
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if ((addr & 1) == 0) {
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return 0xff;
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} else {
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switch(s->cmos_index) {
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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ret = s->cmos_data[s->cmos_index];
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break;
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case RTC_REG_A:
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ret = s->cmos_data[s->cmos_index];
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break;
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case RTC_REG_C:
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ret = s->cmos_data[s->cmos_index];
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pic_set_irq(s->irq, 0);
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s->cmos_data[RTC_REG_C] = 0x00;
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break;
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default:
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ret = s->cmos_data[s->cmos_index];
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break;
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}
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#ifdef DEBUG_CMOS
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printf("cmos: read index=0x%02x val=0x%02x\n",
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s->cmos_index, ret);
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#endif
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return ret;
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}
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}
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static void rtc_set_date_buf(RTCState *s, const struct tm *tm)
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{
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s->buf_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
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s->buf_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
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if (s->cmos_data[RTC_REG_B] & 0x02) {
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/* 24 hour format */
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s->buf_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
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} else {
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/* 12 hour format */
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s->buf_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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if (tm->tm_hour >= 12)
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s->buf_data[RTC_HOURS] |= 0x80;
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}
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s->buf_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
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s->buf_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
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s->buf_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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s->buf_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
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}
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static void rtc_copy_date(RTCState *s)
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{
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s->cmos_data[RTC_SECONDS] = s->buf_data[RTC_SECONDS];
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s->cmos_data[RTC_MINUTES] = s->buf_data[RTC_MINUTES];
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s->cmos_data[RTC_HOURS] = s->buf_data[RTC_HOURS];
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s->cmos_data[RTC_DAY_OF_WEEK] = s->buf_data[RTC_DAY_OF_WEEK];
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s->cmos_data[RTC_DAY_OF_MONTH] = s->buf_data[RTC_DAY_OF_MONTH];
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s->cmos_data[RTC_MONTH] = s->buf_data[RTC_MONTH];
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s->cmos_data[RTC_YEAR] = s->buf_data[RTC_YEAR];
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}
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void rtc_set_memory(RTCState *s, int addr, int val)
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{
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if (addr >= 0 && addr <= 127)
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s->cmos_data[addr] = val;
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}
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void rtc_set_date(RTCState *s, const struct tm *tm)
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{
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s->current_time = mktime((struct tm *)tm);
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rtc_set_date_buf(s, tm);
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rtc_copy_date(s);
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}
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static void rtc_save(QEMUFile *f, void *opaque)
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{
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RTCState *s = opaque;
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qemu_put_buffer(f, s->cmos_data, 128);
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qemu_put_8s(f, &s->cmos_index);
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qemu_put_be32s(f, &s->current_time);
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qemu_put_buffer(f, s->buf_data, 10);
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qemu_put_timer(f, s->periodic_timer);
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qemu_put_be64s(f, &s->next_periodic_time);
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qemu_put_be64s(f, &s->next_second_time);
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qemu_put_timer(f, s->second_timer);
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qemu_put_timer(f, s->second_timer2);
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}
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static int rtc_load(QEMUFile *f, void *opaque, int version_id)
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{
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RTCState *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_buffer(f, s->cmos_data, 128);
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qemu_get_8s(f, &s->cmos_index);
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qemu_get_be32s(f, &s->current_time);
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qemu_get_buffer(f, s->buf_data, 10);
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qemu_get_timer(f, s->periodic_timer);
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qemu_get_be64s(f, &s->next_periodic_time);
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qemu_get_be64s(f, &s->next_second_time);
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qemu_get_timer(f, s->second_timer);
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qemu_get_timer(f, s->second_timer2);
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return 0;
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}
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RTCState *rtc_init(int base, int irq)
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{
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RTCState *s;
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s = qemu_mallocz(sizeof(RTCState));
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if (!s)
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return NULL;
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s->irq = irq;
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s->cmos_data[RTC_REG_A] = 0x26;
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s->cmos_data[RTC_REG_B] = 0x02;
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s->cmos_data[RTC_REG_C] = 0x00;
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s->cmos_data[RTC_REG_D] = 0x80;
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s->periodic_timer = qemu_new_timer(vm_clock,
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rtc_periodic_timer, s);
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s->second_timer = qemu_new_timer(vm_clock,
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rtc_update_second, s);
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s->second_timer2 = qemu_new_timer(vm_clock,
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rtc_update_second2, s);
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s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
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qemu_mod_timer(s->second_timer2, s->next_second_time);
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register_ioport_write(base, 2, 1, cmos_ioport_write, s);
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register_ioport_read(base, 2, 1, cmos_ioport_read, s);
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register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
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return s;
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}
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