dfce81f1b9
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be realized prior to realizing the vCPUs themselves, i.e. long before generic devices are parsed and realized. From a virtualization perspective, the CPUID aspect also means that EPC sections cannot be hotplugged without paravirtualizing the guest kernel (hardware does not support hotplugging as EPC sections must be locked down during pre-boot to provide EPC's security properties). So even though EPC sections could be realized through the generic -devices command, they need to be created much earlier for them to actually be usable by the guest. Place all EPC sections in a contiguous block, somewhat arbitrarily starting after RAM above 4g. Ensuring EPC is in a contiguous region simplifies calculations, e.g. device memory base, PCI hole, etc..., allows dynamic calculation of the total EPC size, e.g. exposing EPC to guests does not require -maxmem, and last but not least allows all of EPC to be enumerated in a single ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8. The new compound properties command for sgx like below: ...... -object memory-backend-epc,id=mem1,size=28M,prealloc=on \ -object memory-backend-epc,id=mem2,size=10M \ -M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2 Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-6-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
307 lines
8.9 KiB
C
307 lines
8.9 KiB
C
#ifndef HW_PC_H
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#define HW_PC_H
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#include "qemu/notify.h"
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#include "qapi/qapi-types-common.h"
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#include "qemu/uuid.h"
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#include "hw/boards.h"
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#include "hw/block/fdc.h"
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#include "hw/block/flash.h"
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#include "hw/i386/x86.h"
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#include "hw/acpi/acpi_dev_interface.h"
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#include "hw/hotplug.h"
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#include "qom/object.h"
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#include "hw/i386/sgx-epc.h"
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#define HPET_INTCAP "hpet-intcap"
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/**
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* PCMachineState:
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* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
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* @boot_cpus: number of present VCPUs
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*/
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typedef struct PCMachineState {
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/*< private >*/
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X86MachineState parent_obj;
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/* <public> */
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/* State for other subsystems/APIs: */
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Notifier machine_done;
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/* Pointers to devices and objects: */
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PCIBus *bus;
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I2CBus *smbus;
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PFlashCFI01 *flash[2];
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ISADevice *pcspk;
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/* Configuration options: */
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uint64_t max_ram_below_4g;
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OnOffAuto vmport;
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bool acpi_build_enabled;
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bool smbus_enabled;
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bool sata_enabled;
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bool pit_enabled;
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bool hpet_enabled;
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bool default_bus_bypass_iommu;
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uint64_t max_fw_size;
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/* ACPI Memory hotplug IO base address */
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hwaddr memhp_io_base;
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SGXEPCState sgx_epc;
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} PCMachineState;
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#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
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#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
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#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
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#define PC_MACHINE_VMPORT "vmport"
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#define PC_MACHINE_SMBUS "smbus"
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#define PC_MACHINE_SATA "sata"
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#define PC_MACHINE_PIT "pit"
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#define PC_MACHINE_MAX_FW_SIZE "max-fw-size"
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/**
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* PCMachineClass:
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*
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* Compat fields:
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*
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* @enforce_aligned_dimm: check that DIMM's address/size is aligned by
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* backend's alignment value if provided
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* @acpi_data_size: Size of the chunk of memory at the top of RAM
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* for the BIOS ACPI tables and other BIOS
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* datastructures.
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* @gigabyte_align: Make sure that guest addresses aligned at
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* 1Gbyte boundaries get mapped to host
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* addresses aligned at 1Gbyte boundaries. This
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* way we can use 1GByte pages in the host.
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*
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*/
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struct PCMachineClass {
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/*< private >*/
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X86MachineClass parent_class;
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/*< public >*/
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/* Device configuration: */
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bool pci_enabled;
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bool kvmclock_enabled;
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const char *default_nic_model;
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/* Compat options: */
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/* Default CPU model version. See x86_cpu_set_default_version(). */
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int default_cpu_version;
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/* ACPI compat: */
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bool has_acpi_build;
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bool rsdp_in_ram;
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int legacy_acpi_table_size;
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unsigned acpi_data_size;
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bool do_not_add_smb_acpi;
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int pci_root_uid;
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/* SMBIOS compat: */
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bool smbios_defaults;
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bool smbios_legacy_mode;
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bool smbios_uuid_encoded;
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/* RAM / address space compat: */
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bool gigabyte_align;
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bool has_reserved_memory;
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bool enforce_aligned_dimm;
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bool broken_reserved_end;
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/* generate legacy CPU hotplug AML */
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bool legacy_cpu_hotplug;
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/* use DMA capable linuxboot option rom */
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bool linuxboot_dma_enabled;
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/* use PVH to load kernels that support this feature */
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bool pvh_enabled;
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/* create kvmclock device even when KVM PV features are not exposed */
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bool kvmclock_create_always;
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};
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#define TYPE_PC_MACHINE "generic-pc-machine"
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OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE)
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/* ioapic.c */
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GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
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/* pc.c */
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extern int fd_bootchk;
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
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void pc_guest_info_init(PCMachineState *pcms);
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#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
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#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
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#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
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#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
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#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
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#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
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#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
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void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
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MemoryRegion *pci_address_space);
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void xen_load_linux(PCMachineState *pcms);
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void pc_memory_init(PCMachineState *pcms,
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MemoryRegion *system_memory,
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MemoryRegion *rom_memory,
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MemoryRegion **ram_memory);
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uint64_t pc_pci_hole64_start(void);
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DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
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void pc_basic_device_init(struct PCMachineState *pcms,
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ISABus *isa_bus, qemu_irq *gsi,
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ISADevice **rtc_state,
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bool create_fdctrl,
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uint32_t hpet_irqs);
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void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
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void pc_cmos_init(PCMachineState *pcms,
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BusState *ide0, BusState *ide1,
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ISADevice *s);
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void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
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void pc_pci_device_init(PCIBus *pci_bus);
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typedef void (*cpu_set_smm_t)(int smm, void *arg);
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void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
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ISADevice *pc_find_fdc0(void);
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/* port92.c */
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#define PORT92_A20_LINE "a20"
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#define TYPE_PORT92 "port92"
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/* pc_sysfw.c */
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void pc_system_flash_create(PCMachineState *pcms);
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void pc_system_flash_cleanup_unused(PCMachineState *pcms);
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void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
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bool pc_system_ovmf_table_find(const char *entry, uint8_t **data,
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int *data_len);
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void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size);
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/* acpi-build.c */
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void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
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const CPUArchIdList *apic_ids, GArray *entry);
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extern GlobalProperty pc_compat_6_1[];
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extern const size_t pc_compat_6_1_len;
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extern GlobalProperty pc_compat_6_0[];
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extern const size_t pc_compat_6_0_len;
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extern GlobalProperty pc_compat_5_2[];
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extern const size_t pc_compat_5_2_len;
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extern GlobalProperty pc_compat_5_1[];
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extern const size_t pc_compat_5_1_len;
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extern GlobalProperty pc_compat_5_0[];
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extern const size_t pc_compat_5_0_len;
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extern GlobalProperty pc_compat_4_2[];
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extern const size_t pc_compat_4_2_len;
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extern GlobalProperty pc_compat_4_1[];
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extern const size_t pc_compat_4_1_len;
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extern GlobalProperty pc_compat_4_0[];
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extern const size_t pc_compat_4_0_len;
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extern GlobalProperty pc_compat_3_1[];
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extern const size_t pc_compat_3_1_len;
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extern GlobalProperty pc_compat_3_0[];
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extern const size_t pc_compat_3_0_len;
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extern GlobalProperty pc_compat_2_12[];
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extern const size_t pc_compat_2_12_len;
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extern GlobalProperty pc_compat_2_11[];
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extern const size_t pc_compat_2_11_len;
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extern GlobalProperty pc_compat_2_10[];
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extern const size_t pc_compat_2_10_len;
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extern GlobalProperty pc_compat_2_9[];
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extern const size_t pc_compat_2_9_len;
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extern GlobalProperty pc_compat_2_8[];
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extern const size_t pc_compat_2_8_len;
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extern GlobalProperty pc_compat_2_7[];
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extern const size_t pc_compat_2_7_len;
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extern GlobalProperty pc_compat_2_6[];
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extern const size_t pc_compat_2_6_len;
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extern GlobalProperty pc_compat_2_5[];
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extern const size_t pc_compat_2_5_len;
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extern GlobalProperty pc_compat_2_4[];
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extern const size_t pc_compat_2_4_len;
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extern GlobalProperty pc_compat_2_3[];
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extern const size_t pc_compat_2_3_len;
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extern GlobalProperty pc_compat_2_2[];
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extern const size_t pc_compat_2_2_len;
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extern GlobalProperty pc_compat_2_1[];
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extern const size_t pc_compat_2_1_len;
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extern GlobalProperty pc_compat_2_0[];
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extern const size_t pc_compat_2_0_len;
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extern GlobalProperty pc_compat_1_7[];
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extern const size_t pc_compat_1_7_len;
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extern GlobalProperty pc_compat_1_6[];
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extern const size_t pc_compat_1_6_len;
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extern GlobalProperty pc_compat_1_5[];
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extern const size_t pc_compat_1_5_len;
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extern GlobalProperty pc_compat_1_4[];
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extern const size_t pc_compat_1_4_len;
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/* Helper for setting model-id for CPU models that changed model-id
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* depending on QEMU versions up to QEMU 2.4.
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*/
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#define PC_CPU_MODEL_IDS(v) \
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{ "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
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{ "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
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{ "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
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#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
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static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
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{ \
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MachineClass *mc = MACHINE_CLASS(oc); \
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optsfn(mc); \
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mc->init = initfn; \
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} \
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static const TypeInfo pc_machine_type_##suffix = { \
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.name = namestr TYPE_MACHINE_SUFFIX, \
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.parent = TYPE_PC_MACHINE, \
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.class_init = pc_machine_##suffix##_class_init, \
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}; \
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static void pc_machine_init_##suffix(void) \
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{ \
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type_register(&pc_machine_type_##suffix); \
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} \
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type_init(pc_machine_init_##suffix)
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extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
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#endif
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