qemu/target
Tao Wu df16af8741 target/i386: hax: Move x86_update_hflags.
x86_update_hflags reference env->efer which is updated in hax_get_msrs,
so it has to be called after hax_get_msrs. This fix the bug that sometimes
dump_state show 32 bits regs even in 64 bits mode.

Signed-off-by: Tao Wu <lepton@google.com>
Message-Id: <20180110195056.85403-3-lepton@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-16 14:54:51 +01:00
..
alpha tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
arm target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions 2018-01-11 13:25:40 +00:00
cris tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
hppa tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
i386 target/i386: hax: Move x86_update_hflags. 2018-01-16 14:54:51 +01:00
lm32 tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
m68k -----BEGIN PGP SIGNATURE----- 2018-01-08 21:39:44 +00:00
microblaze tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
mips tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
moxie target/moxie: Fix tlb_fill 2017-12-27 17:20:44 -08:00
nios2 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
openrisc target/*helper: don't check retaddr before calling cpu_restore_state 2017-12-27 17:20:44 -08:00
ppc target/ppc: more use of the PPC_*() macros 2018-01-10 12:53:00 +11:00
s390x tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
sh4 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
sparc target/sparc: remove MemoryRegionSection check code from sparc_cpu_get_phys_page_debug() 2018-01-09 21:31:31 +00:00
tilegx tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
tricore target/*helper: don't check retaddr before calling cpu_restore_state 2017-12-27 17:20:44 -08:00
unicore32 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
xtensa target/xtensa: implement disassembler 2018-01-09 09:55:39 -08:00