Alexey Baturo dec19f6813 target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V ...

Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220717101543.478533-2-space.monkey.delivers@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-09-07 09:18:32 +02:00

..

insn_trans

target/riscv: Minimize the calls to decode_save_opc

2022-07-03 10:03:20 +10:00

arch_dump.c

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bitmanip_helper.c

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common-semi-target.h

semihosting: Split out common-semi-target.h

2022-06-28 04:35:07 +05:30

cpu_bits.h

target/riscv: Update default priority table for local interrupts

2022-07-03 10:03:20 +10:00

cpu_helper.c

target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

2022-09-07 09:18:32 +02:00

cpu_user.h

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cpu-param.h

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cpu.c

target/riscv: Fix checks in hmode/hmode32

2022-09-07 09:18:32 +02:00

cpu.h

target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

2022-09-07 09:18:32 +02:00

crypto_helper.c

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csr.c

target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check

2022-09-07 09:18:32 +02:00

debug.c

target/riscv/debug.c: keep experimental rv128 support working

2022-06-10 09:31:42 +10:00

debug.h

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fpu_helper.c

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gdbstub.c

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helper.h

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insn16.decode

target/riscv: fix shifts shamt value for rv128c

2022-09-07 09:18:32 +02:00

insn32.decode

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instmap.h

target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()

2022-09-07 09:18:32 +02:00

internals.h

target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

2022-06-10 09:31:42 +10:00

Kconfig

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kvm_riscv.h

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kvm-stub.c

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kvm.c

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m128_helper.c

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machine.c

target/riscv: Support mcycle/minstret write operation

2022-07-03 10:03:20 +10:00

meson.build

meson: remove dead code

2022-09-01 07:42:37 +02:00

monitor.c

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op_helper.c

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pmp.c

target/riscv/pmp: guard against PMP ranges with a negative size

2022-07-03 10:03:20 +10:00

pmp.h

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pmu.c

target/riscv: Support mcycle/minstret write operation

2022-07-03 10:03:20 +10:00

pmu.h

target/riscv: Support mcycle/minstret write operation

2022-07-03 10:03:20 +10:00

sbi_ecall_interface.h

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trace-events

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trace.h

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translate.c

target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V

2022-09-07 09:18:32 +02:00

vector_helper.c

target/riscv: rvv: Add tail agnostic for vector permutation instructions

2022-06-10 09:31:42 +10:00

XVentanaCondOps.decode

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