35a60a20f0
Debug exceptions that target AArch32 Hyp mode are reported differently
than on AAarch64. Internally, Qemu uses the AArch64 syndromes. Therefore
such exceptions need to be either converted to a prefetch abort
(breakpoints, vector catch) or a data abort (watchpoints).
Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Klötzke <jan.kloetzke@kernkonzept.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240127202758.3326381-1-jan.kloetzke@kernkonzept.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit f670be1aad)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
358 lines
12 KiB
C
358 lines
12 KiB
C
/*
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* QEMU ARM CPU -- syndrome functions and types
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*
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* Copyright (c) 2014 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*
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* This header defines functions, types, etc which need to be shared
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* between different source files within target/arm/ but which are
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* private to it and not required by the rest of QEMU.
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*/
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#ifndef TARGET_ARM_SYNDROME_H
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#define TARGET_ARM_SYNDROME_H
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#include "qemu/bitops.h"
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/* Valid Syndrome Register EC field values */
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enum arm_exception_class {
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EC_UNCATEGORIZED = 0x00,
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EC_WFX_TRAP = 0x01,
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EC_CP15RTTRAP = 0x03,
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EC_CP15RRTTRAP = 0x04,
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EC_CP14RTTRAP = 0x05,
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EC_CP14DTTRAP = 0x06,
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EC_ADVSIMDFPACCESSTRAP = 0x07,
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EC_FPIDTRAP = 0x08,
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EC_PACTRAP = 0x09,
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EC_BXJTRAP = 0x0a,
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EC_CP14RRTTRAP = 0x0c,
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EC_BTITRAP = 0x0d,
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EC_ILLEGALSTATE = 0x0e,
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EC_AA32_SVC = 0x11,
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EC_AA32_HVC = 0x12,
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EC_AA32_SMC = 0x13,
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EC_AA64_SVC = 0x15,
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EC_AA64_HVC = 0x16,
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EC_AA64_SMC = 0x17,
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EC_SYSTEMREGISTERTRAP = 0x18,
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EC_SVEACCESSTRAP = 0x19,
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EC_ERETTRAP = 0x1a,
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EC_PACFAIL = 0x1c,
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EC_SMETRAP = 0x1d,
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EC_GPC = 0x1e,
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EC_INSNABORT = 0x20,
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EC_INSNABORT_SAME_EL = 0x21,
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EC_PCALIGNMENT = 0x22,
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EC_DATAABORT = 0x24,
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EC_DATAABORT_SAME_EL = 0x25,
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EC_SPALIGNMENT = 0x26,
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EC_MOP = 0x27,
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EC_AA32_FPTRAP = 0x28,
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EC_AA64_FPTRAP = 0x2c,
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EC_SERROR = 0x2f,
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EC_BREAKPOINT = 0x30,
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EC_BREAKPOINT_SAME_EL = 0x31,
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EC_SOFTWARESTEP = 0x32,
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EC_SOFTWARESTEP_SAME_EL = 0x33,
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EC_WATCHPOINT = 0x34,
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EC_WATCHPOINT_SAME_EL = 0x35,
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EC_AA32_BKPT = 0x38,
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EC_VECTORCATCH = 0x3a,
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EC_AA64_BKPT = 0x3c,
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};
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typedef enum {
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SME_ET_AccessTrap,
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SME_ET_Streaming,
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SME_ET_NotStreaming,
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SME_ET_InactiveZA,
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} SMEExceptionType;
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#define ARM_EL_EC_LENGTH 6
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#define ARM_EL_EC_SHIFT 26
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#define ARM_EL_IL_SHIFT 25
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#define ARM_EL_ISV_SHIFT 24
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#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
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#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
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static inline uint32_t syn_get_ec(uint32_t syn)
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{
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return syn >> ARM_EL_EC_SHIFT;
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}
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static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec)
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{
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return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec);
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}
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/*
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* Utility functions for constructing various kinds of syndrome value.
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* Note that in general we follow the AArch64 syndrome values; in a
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* few cases the value in HSR for exceptions taken to AArch32 Hyp
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* mode differs slightly, and we fix this up when populating HSR in
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* arm_cpu_do_interrupt_aarch32_hyp().
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* The exception is FP/SIMD access traps -- these report extra information
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* when taking an exception to AArch32. For those we include the extra coproc
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* and TA fields, and mask them out when taking the exception to AArch64.
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*/
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static inline uint32_t syn_uncategorized(void)
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{
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return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_aa64_svc(uint32_t imm16)
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{
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return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa64_hvc(uint32_t imm16)
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{
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return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa64_smc(uint32_t imm16)
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{
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return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
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{
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return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
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| (is_16bit ? 0 : ARM_EL_IL);
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}
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static inline uint32_t syn_aa32_hvc(uint32_t imm16)
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{
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return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa32_smc(void)
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{
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return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
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{
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return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
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{
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return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
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| (is_16bit ? 0 : ARM_EL_IL);
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}
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static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
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int crn, int crm, int rt,
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int isread)
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{
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return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
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| (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
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| (crm << 1) | isread;
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}
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static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
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int crn, int crm, int rt, int isread,
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bool is_16bit)
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{
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return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
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| (crn << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
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int crn, int crm, int rt, int isread,
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bool is_16bit)
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{
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return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
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| (crn << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
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int rt, int rt2, int isread,
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bool is_16bit)
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{
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return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc1 << 16)
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| (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
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int rt, int rt2, int isread,
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bool is_16bit)
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{
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return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc1 << 16)
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| (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
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int coproc)
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{
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/* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
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return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | coproc;
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}
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static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
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{
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/* AArch32 SIMD trap: TA == 1 coproc == 0 */
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return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (1 << 5);
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}
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static inline uint32_t syn_sve_access_trap(void)
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{
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return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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/*
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* eret_op is bits [1:0] of the ERET instruction, so:
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* 0 for ERET, 2 for ERETAA, 3 for ERETAB.
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*/
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static inline uint32_t syn_erettrap(int eret_op)
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{
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return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
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}
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static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
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{
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return (EC_SMETRAP << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL) | etype;
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}
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static inline uint32_t syn_pacfail(bool data, int keynumber)
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{
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int error_code = (data << 1) | keynumber;
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return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code;
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}
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static inline uint32_t syn_pactrap(void)
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{
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return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_btitrap(int btype)
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{
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return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype;
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}
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static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
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{
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return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
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(cv << 24) | (cond << 20) | rm;
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}
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static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc,
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int cm, int s1ptw, int wnr, int fsc)
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{
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/* TODO: FEAT_NV2 adds VNCR */
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return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21)
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| (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7)
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| (wnr << 6) | fsc;
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}
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static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
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{
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return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
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}
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static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv,
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int ea, int cm, int s1ptw,
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int wnr, int fsc)
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{
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return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| ARM_EL_IL
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| (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7)
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| (wnr << 6) | fsc;
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}
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static inline uint32_t syn_data_abort_with_iss(int same_el,
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int sas, int sse, int srt,
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int sf, int ar,
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int ea, int cm, int s1ptw,
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int wnr, int fsc,
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bool is_16bit)
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{
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return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (is_16bit ? 0 : ARM_EL_IL)
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| ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
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| (sf << 15) | (ar << 14)
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| (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
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}
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static inline uint32_t syn_swstep(int same_el, int isv, int ex)
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{
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return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
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}
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static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
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{
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return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
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}
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static inline uint32_t syn_breakpoint(int same_el)
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{
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return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| ARM_EL_IL | 0x22;
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}
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static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
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{
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return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
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(is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
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(cv << 24) | (cond << 20) | ti;
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}
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static inline uint32_t syn_illegalstate(void)
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{
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return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_pcalignment(void)
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{
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return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_serror(uint32_t extra)
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{
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return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
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}
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static inline uint32_t syn_mop(bool is_set, bool is_setg, int options,
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bool epilogue, bool wrong_option, bool option_a,
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int destreg, int srcreg, int sizereg)
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{
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return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
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(is_set << 24) | (is_setg << 23) | (options << 19) |
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(epilogue << 18) | (wrong_option << 17) | (option_a << 16) |
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(destreg << 10) | (srcreg << 5) | sizereg;
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}
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#endif /* TARGET_ARM_SYNDROME_H */
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