de343bb632
The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other bits of glue in the system. This commit provides the initial skeleton of the device, implementing just the ID registers, and a couple of read-only read-as-zero registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-16-peter.maydell@linaro.org
449 lines
11 KiB
C
449 lines
11 KiB
C
/*
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* Arm IoT Kit security controller
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/iotkit-secctl.h"
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/* Registers in the secure privilege control block */
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REG32(SECRESPCFG, 0x10)
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REG32(NSCCFG, 0x14)
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REG32(SECMPCINTSTATUS, 0x1c)
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REG32(SECPPCINTSTAT, 0x20)
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REG32(SECPPCINTCLR, 0x24)
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REG32(SECPPCINTEN, 0x28)
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REG32(SECMSCINTSTAT, 0x30)
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REG32(SECMSCINTCLR, 0x34)
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REG32(SECMSCINTEN, 0x38)
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REG32(BRGINTSTAT, 0x40)
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REG32(BRGINTCLR, 0x44)
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REG32(BRGINTEN, 0x48)
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REG32(AHBNSPPC0, 0x50)
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REG32(AHBNSPPCEXP0, 0x60)
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REG32(AHBNSPPCEXP1, 0x64)
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REG32(AHBNSPPCEXP2, 0x68)
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REG32(AHBNSPPCEXP3, 0x6c)
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REG32(APBNSPPC0, 0x70)
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REG32(APBNSPPC1, 0x74)
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REG32(APBNSPPCEXP0, 0x80)
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REG32(APBNSPPCEXP1, 0x84)
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REG32(APBNSPPCEXP2, 0x88)
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REG32(APBNSPPCEXP3, 0x8c)
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REG32(AHBSPPPC0, 0x90)
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REG32(AHBSPPPCEXP0, 0xa0)
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REG32(AHBSPPPCEXP1, 0xa4)
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REG32(AHBSPPPCEXP2, 0xa8)
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REG32(AHBSPPPCEXP3, 0xac)
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REG32(APBSPPPC0, 0xb0)
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REG32(APBSPPPC1, 0xb4)
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REG32(APBSPPPCEXP0, 0xc0)
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REG32(APBSPPPCEXP1, 0xc4)
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REG32(APBSPPPCEXP2, 0xc8)
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REG32(APBSPPPCEXP3, 0xcc)
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REG32(NSMSCEXP, 0xd0)
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REG32(PID4, 0xfd0)
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REG32(PID5, 0xfd4)
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REG32(PID6, 0xfd8)
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REG32(PID7, 0xfdc)
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REG32(PID0, 0xfe0)
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REG32(PID1, 0xfe4)
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REG32(PID2, 0xfe8)
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REG32(PID3, 0xfec)
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REG32(CID0, 0xff0)
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REG32(CID1, 0xff4)
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REG32(CID2, 0xff8)
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REG32(CID3, 0xffc)
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/* Registers in the non-secure privilege control block */
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REG32(AHBNSPPPC0, 0x90)
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REG32(AHBNSPPPCEXP0, 0xa0)
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REG32(AHBNSPPPCEXP1, 0xa4)
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REG32(AHBNSPPPCEXP2, 0xa8)
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REG32(AHBNSPPPCEXP3, 0xac)
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REG32(APBNSPPPC0, 0xb0)
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REG32(APBNSPPPC1, 0xb4)
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REG32(APBNSPPPCEXP0, 0xc0)
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REG32(APBNSPPPCEXP1, 0xc4)
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REG32(APBNSPPPCEXP2, 0xc8)
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REG32(APBNSPPPCEXP3, 0xcc)
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/* PID and CID registers are also present in the NS block */
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static const uint8_t iotkit_secctl_s_idregs[] = {
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0x04, 0x00, 0x00, 0x00,
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0x52, 0xb8, 0x0b, 0x00,
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0x0d, 0xf0, 0x05, 0xb1,
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};
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static const uint8_t iotkit_secctl_ns_idregs[] = {
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0x04, 0x00, 0x00, 0x00,
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0x53, 0xb8, 0x0b, 0x00,
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0x0d, 0xf0, 0x05, 0xb1,
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};
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static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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uint64_t r;
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uint32_t offset = addr & ~0x3;
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switch (offset) {
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case A_AHBNSPPC0:
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case A_AHBSPPPC0:
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r = 0;
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break;
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case A_SECRESPCFG:
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case A_NSCCFG:
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case A_SECMPCINTSTATUS:
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case A_SECPPCINTSTAT:
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case A_SECPPCINTEN:
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case A_SECMSCINTSTAT:
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case A_SECMSCINTEN:
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case A_BRGINTSTAT:
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case A_BRGINTEN:
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case A_AHBNSPPCEXP0:
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case A_AHBNSPPCEXP1:
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case A_AHBNSPPCEXP2:
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case A_AHBNSPPCEXP3:
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case A_APBNSPPC0:
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case A_APBNSPPC1:
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case A_APBNSPPCEXP0:
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case A_APBNSPPCEXP1:
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case A_APBNSPPCEXP2:
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case A_APBNSPPCEXP3:
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case A_AHBSPPPCEXP0:
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case A_AHBSPPPCEXP1:
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case A_AHBSPPPCEXP2:
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case A_AHBSPPPCEXP3:
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case A_APBSPPPC0:
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case A_APBSPPPC1:
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case A_APBSPPPCEXP0:
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case A_APBSPPPCEXP1:
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case A_APBSPPPCEXP2:
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case A_APBSPPPCEXP3:
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case A_NSMSCEXP:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl S block read: "
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"unimplemented offset 0x%x\n", offset);
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r = 0;
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break;
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case A_PID4:
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case A_PID5:
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case A_PID6:
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case A_PID7:
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case A_PID0:
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case A_PID1:
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case A_PID2:
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case A_PID3:
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case A_CID0:
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case A_CID1:
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case A_CID2:
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case A_CID3:
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r = iotkit_secctl_s_idregs[(offset - A_PID4) / 4];
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break;
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case A_SECPPCINTCLR:
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case A_SECMSCINTCLR:
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case A_BRGINTCLR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl S block read: write-only offset 0x%x\n",
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offset);
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r = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl S block read: bad offset 0x%x\n", offset);
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r = 0;
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break;
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}
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if (size != 4) {
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/* None of our registers are access-sensitive, so just pull the right
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* byte out of the word read result.
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*/
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r = extract32(r, (addr & 3) * 8, size * 8);
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}
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trace_iotkit_secctl_s_read(offset, r, size);
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*pdata = r;
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return MEMTX_OK;
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}
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static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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uint32_t offset = addr;
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trace_iotkit_secctl_s_write(offset, value, size);
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if (size != 4) {
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/* Byte and halfword writes are ignored */
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl S block write: bad size, ignored\n");
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return MEMTX_OK;
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}
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switch (offset) {
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case A_SECRESPCFG:
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case A_NSCCFG:
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case A_SECPPCINTCLR:
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case A_SECPPCINTEN:
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case A_SECMSCINTCLR:
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case A_SECMSCINTEN:
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case A_BRGINTCLR:
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case A_BRGINTEN:
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case A_AHBNSPPCEXP0:
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case A_AHBNSPPCEXP1:
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case A_AHBNSPPCEXP2:
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case A_AHBNSPPCEXP3:
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case A_APBNSPPC0:
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case A_APBNSPPC1:
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case A_APBNSPPCEXP0:
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case A_APBNSPPCEXP1:
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case A_APBNSPPCEXP2:
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case A_APBNSPPCEXP3:
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case A_AHBSPPPCEXP0:
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case A_AHBSPPPCEXP1:
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case A_AHBSPPPCEXP2:
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case A_AHBSPPPCEXP3:
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case A_APBSPPPC0:
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case A_APBSPPPC1:
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case A_APBSPPPCEXP0:
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case A_APBSPPPCEXP1:
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case A_APBSPPPCEXP2:
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case A_APBSPPPCEXP3:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl S block write: "
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"unimplemented offset 0x%x\n", offset);
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break;
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case A_SECMPCINTSTATUS:
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case A_SECPPCINTSTAT:
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case A_SECMSCINTSTAT:
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case A_BRGINTSTAT:
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case A_AHBNSPPC0:
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case A_AHBSPPPC0:
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case A_NSMSCEXP:
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case A_PID4:
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case A_PID5:
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case A_PID6:
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case A_PID7:
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case A_PID0:
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case A_PID1:
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case A_PID2:
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case A_PID3:
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case A_CID0:
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case A_CID1:
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case A_CID2:
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case A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SecCtl S block write: "
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"read-only offset 0x%x\n", offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl S block write: bad offset 0x%x\n",
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offset);
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break;
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}
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return MEMTX_OK;
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}
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static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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uint64_t r;
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uint32_t offset = addr & ~0x3;
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switch (offset) {
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case A_AHBNSPPPC0:
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r = 0;
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break;
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case A_AHBNSPPPCEXP0:
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case A_AHBNSPPPCEXP1:
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case A_AHBNSPPPCEXP2:
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case A_AHBNSPPPCEXP3:
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case A_APBNSPPPC0:
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case A_APBNSPPPC1:
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case A_APBNSPPPCEXP0:
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case A_APBNSPPPCEXP1:
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case A_APBNSPPPCEXP2:
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case A_APBNSPPPCEXP3:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl NS block read: "
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"unimplemented offset 0x%x\n", offset);
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break;
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case A_PID4:
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case A_PID5:
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case A_PID6:
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case A_PID7:
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case A_PID0:
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case A_PID1:
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case A_PID2:
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case A_PID3:
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case A_CID0:
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case A_CID1:
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case A_CID2:
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case A_CID3:
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r = iotkit_secctl_ns_idregs[(offset - A_PID4) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl NS block write: bad offset 0x%x\n",
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offset);
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r = 0;
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break;
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}
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if (size != 4) {
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/* None of our registers are access-sensitive, so just pull the right
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* byte out of the word read result.
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*/
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r = extract32(r, (addr & 3) * 8, size * 8);
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}
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trace_iotkit_secctl_ns_read(offset, r, size);
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*pdata = r;
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return MEMTX_OK;
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}
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static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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uint32_t offset = addr;
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trace_iotkit_secctl_ns_write(offset, value, size);
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if (size != 4) {
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/* Byte and halfword writes are ignored */
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl NS block write: bad size, ignored\n");
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return MEMTX_OK;
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}
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switch (offset) {
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case A_AHBNSPPPCEXP0:
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case A_AHBNSPPPCEXP1:
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case A_AHBNSPPPCEXP2:
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case A_AHBNSPPPCEXP3:
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case A_APBNSPPPC0:
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case A_APBNSPPPC1:
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case A_APBNSPPPCEXP0:
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case A_APBNSPPPCEXP1:
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case A_APBNSPPPCEXP2:
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case A_APBNSPPPCEXP3:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl NS block write: "
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"unimplemented offset 0x%x\n", offset);
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break;
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case A_AHBNSPPPC0:
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case A_PID4:
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case A_PID5:
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case A_PID6:
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case A_PID7:
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case A_PID0:
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case A_PID1:
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case A_PID2:
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case A_PID3:
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case A_CID0:
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case A_CID1:
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case A_CID2:
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case A_CID3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IoTKit SecCtl NS block write: "
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"read-only offset 0x%x\n", offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"IotKit SecCtl NS block write: bad offset 0x%x\n",
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offset);
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break;
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps iotkit_secctl_s_ops = {
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.read_with_attrs = iotkit_secctl_s_read,
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.write_with_attrs = iotkit_secctl_s_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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};
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static const MemoryRegionOps iotkit_secctl_ns_ops = {
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.read_with_attrs = iotkit_secctl_ns_read,
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.write_with_attrs = iotkit_secctl_ns_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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};
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static void iotkit_secctl_reset(DeviceState *dev)
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{
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}
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static void iotkit_secctl_init(Object *obj)
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{
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IoTKitSecCtl *s = IOTKIT_SECCTL(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops,
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s, "iotkit-secctl-s-regs", 0x1000);
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memory_region_init_io(&s->ns_regs, obj, &iotkit_secctl_ns_ops,
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s, "iotkit-secctl-ns-regs", 0x1000);
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sysbus_init_mmio(sbd, &s->s_regs);
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sysbus_init_mmio(sbd, &s->ns_regs);
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}
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static const VMStateDescription iotkit_secctl_vmstate = {
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.name = "iotkit-secctl",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_END_OF_LIST()
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}
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};
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static void iotkit_secctl_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &iotkit_secctl_vmstate;
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dc->reset = iotkit_secctl_reset;
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}
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static const TypeInfo iotkit_secctl_info = {
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.name = TYPE_IOTKIT_SECCTL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IoTKitSecCtl),
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.instance_init = iotkit_secctl_init,
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.class_init = iotkit_secctl_class_init,
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};
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static void iotkit_secctl_register_types(void)
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{
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type_register_static(&iotkit_secctl_info);
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}
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type_init(iotkit_secctl_register_types);
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