qemu/target/ppc/translate
Philippe Mathieu-Daudé dd977e4f45 target/ppc: Optimize x[sv]xsigdp using deposit_i64()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20190309214255.9952-3-f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12 14:33:05 +11:00
..
dfp-impl.inc.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
dfp-ops.inc.c
fp-impl.inc.c target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access 2019-01-09 09:28:13 +11:00
fp-ops.inc.c target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
spe-impl.inc.c
spe-ops.inc.c
vmx-impl.inc.c target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64() 2019-03-12 14:33:04 +11:00
vmx-ops.inc.c Changes requirement for "vsubsbs" instruction 2018-12-21 09:29:12 +11:00
vsx-impl.inc.c target/ppc: Optimize x[sv]xsigdp using deposit_i64() 2019-03-12 14:33:05 +11:00
vsx-ops.inc.c target-ppc: Add xscvqpudz and xscvqpuwz instructions 2017-02-22 11:28:28 +11:00