e96efcfcb1
and parallel CFI flash driver. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
578 lines
19 KiB
C
578 lines
19 KiB
C
/*
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* QEMU PPC CHRP/PMAC hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define BIOS_FILENAME "ppc_rom.bin"
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#define VGABIOS_FILENAME "video.x"
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#define NVRAM_SIZE 0x2000
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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NVRAM */
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static int dbdma_mem_index;
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static int cuda_mem_index;
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static int ide0_mem_index = -1;
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static int ide1_mem_index = -1;
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static int openpic_mem_index = -1;
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static int heathrow_pic_mem_index = -1;
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static int macio_nvram_mem_index = -1;
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/* DBDMA: currently no op - should suffice right now */
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static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
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}
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static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
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{
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printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
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return 0;
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}
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static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc *dbdma_write[] = {
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&dbdma_writeb,
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&dbdma_writew,
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&dbdma_writel,
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};
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static CPUReadMemoryFunc *dbdma_read[] = {
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&dbdma_readb,
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&dbdma_readw,
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&dbdma_readl,
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};
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/* macio style NVRAM device */
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typedef struct MacIONVRAMState {
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uint8_t data[0x2000];
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} MacIONVRAMState;
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static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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MacIONVRAMState *s = opaque;
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addr = (addr >> 4) & 0x1fff;
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s->data[addr] = value;
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// printf("macio_nvram_writeb %04x = %02x\n", addr, value);
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}
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static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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MacIONVRAMState *s = opaque;
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uint32_t value;
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addr = (addr >> 4) & 0x1fff;
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value = s->data[addr];
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// printf("macio_nvram_readb %04x = %02x\n", addr, value);
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return value;
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}
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static CPUWriteMemoryFunc *macio_nvram_write[] = {
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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&macio_nvram_writeb,
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};
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static CPUReadMemoryFunc *macio_nvram_read[] = {
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&macio_nvram_readb,
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&macio_nvram_readb,
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&macio_nvram_readb,
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};
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static MacIONVRAMState *macio_nvram_init(void)
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{
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MacIONVRAMState *s;
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s = qemu_mallocz(sizeof(MacIONVRAMState));
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if (!s)
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return NULL;
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macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
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macio_nvram_write, s);
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return s;
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}
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static void macio_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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if (heathrow_pic_mem_index >= 0) {
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cpu_register_physical_memory(addr + 0x00000, 0x1000,
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heathrow_pic_mem_index);
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}
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cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
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if (ide0_mem_index >= 0)
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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if (ide1_mem_index >= 0)
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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if (openpic_mem_index >= 0) {
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cpu_register_physical_memory(addr + 0x40000, 0x40000,
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openpic_mem_index);
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}
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if (macio_nvram_mem_index >= 0)
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cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
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}
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static void macio_init(PCIBus *bus, int device_id)
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{
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PCIDevice *d;
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d = pci_register_device(bus, "macio", sizeof(PCIDevice),
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-1, NULL, NULL);
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/* Note: this code is strongly inspirated from the corresponding code
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in PearPC */
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d->config[0x00] = 0x6b; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = device_id;
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d->config[0x03] = device_id >> 8;
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d->config[0x0a] = 0x00; // class_sub = pci2pci
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d->config[0x0b] = 0xff; // class_base = bridge
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d->config[0x0e] = 0x00; // header_type
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d->config[0x3d] = 0x01; // interrupt on pin 1
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dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
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pci_register_io_region(d, 0, 0x80000,
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PCI_ADDRESS_SPACE_MEM, macio_map);
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}
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/* UniN device */
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static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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}
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static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc *unin_write[] = {
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&unin_writel,
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&unin_writel,
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&unin_writel,
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};
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static CPUReadMemoryFunc *unin_read[] = {
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&unin_readl,
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&unin_readl,
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&unin_readl,
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};
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/* temporary frame buffer OSI calls for the video.x driver. The right
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solution is to modify the driver to use VGA PCI I/Os */
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static int vga_osi_call(CPUState *env)
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{
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static int vga_vbl_enabled;
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int linesize;
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// printf("osi_call R5=%d\n", env->gpr[5]);
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/* same handler as PearPC, coming from the original MOL video
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driver. */
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switch(env->gpr[5]) {
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case 4:
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break;
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case 28: /* set_vmode */
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if (env->gpr[6] != 1 || env->gpr[7] != 0)
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env->gpr[3] = 1;
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else
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env->gpr[3] = 0;
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break;
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case 29: /* get_vmode_info */
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if (env->gpr[6] != 0) {
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if (env->gpr[6] != 1 || env->gpr[7] != 0) {
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env->gpr[3] = 1;
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break;
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}
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}
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env->gpr[3] = 0;
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env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
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env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
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env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
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env->gpr[7] = 85 << 16; /* refresh rate */
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env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
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linesize = ((graphic_depth + 7) >> 3) * graphic_width;
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linesize = (linesize + 3) & ~3;
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env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
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break;
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case 31: /* set_video power */
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env->gpr[3] = 0;
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break;
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case 39: /* video_ctrl */
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if (env->gpr[6] == 0 || env->gpr[6] == 1)
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vga_vbl_enabled = env->gpr[6];
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env->gpr[3] = 0;
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break;
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case 47:
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break;
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case 59: /* set_color */
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/* R6 = index, R7 = RGB */
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env->gpr[3] = 0;
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break;
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case 64: /* get color */
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/* R6 = index */
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env->gpr[3] = 0;
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break;
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case 116: /* set hwcursor */
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
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break;
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}
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return 1; /* osi_call handled */
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}
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static uint8_t nvram_chksum(const uint8_t *buf, int n)
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{
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int sum, i;
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sum = 0;
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for(i = 0; i < n; i++)
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sum += buf[i];
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return (sum & 0xff) + (sum >> 8);
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}
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/* set a free Mac OS NVRAM partition */
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void pmac_format_nvram_partition(uint8_t *buf, int len)
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{
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char partition_name[12] = "wwwwwwwwwwww";
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buf[0] = 0x7f; /* free partition magic */
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buf[1] = 0; /* checksum */
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buf[2] = len >> 8;
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buf[3] = len;
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memcpy(buf + 4, partition_name, 12);
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buf[1] = nvram_chksum(buf, 16);
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}
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/* PowerPC CHRP hardware initialisation */
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static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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int snapshot,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model,
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int is_heathrow)
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{
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CPUState *env, *envs[MAX_CPUS];
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char buf[1024];
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qemu_irq *pic, **openpic_irqs;
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m48t59_t *nvram;
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int unin_memory;
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int linux_boot, i;
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unsigned long bios_offset, vga_bios_offset;
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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ppc_def_t *def;
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PCIBus *pci_bus;
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const char *arch_name;
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int vga_bios_size, bios_size;
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qemu_irq *dummy_irq;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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env = cpu_init();
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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/* Default CPU is a generic 74x/75x */
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if (cpu_model == NULL)
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cpu_model = "750";
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/* XXX: CPU model (or PVR) should be provided on command line */
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// ppc_find_by_name("750gx", &def); // Linux boot OK
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// ppc_find_by_name("750fx", &def); // Linux boot OK
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/* Linux does not boot on 750cxe (and probably other 750cx based)
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* because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
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*/
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ppc_find_by_name(cpu_model, &def);
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if (def == NULL) {
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cpu_abort(env, "Unable to find PowerPC CPU definition\n");
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}
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for (i = 0; i < smp_cpus; i++) {
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cpu_ppc_register(env, def);
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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env->osi_call = vga_osi_call;
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envs[i] = env;
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}
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
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exit(1);
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}
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bios_size = (bios_size + 0xfff) & ~0xfff;
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cpu_register_physical_memory((uint32_t)(-bios_size),
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bios_size, bios_offset | IO_MEM_ROM);
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/* allocate and load VGA BIOS */
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vga_bios_offset = bios_offset + bios_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
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vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
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if (vga_bios_size < 0) {
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/* if no bios is present, we can still work */
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fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
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vga_bios_size = 0;
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} else {
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/* set a specific header (XXX: find real Apple format for NDRV
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drivers) */
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phys_ram_base[vga_bios_offset] = 'N';
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phys_ram_base[vga_bios_offset + 1] = 'D';
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phys_ram_base[vga_bios_offset + 2] = 'R';
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phys_ram_base[vga_bios_offset + 3] = 'V';
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cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
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vga_bios_size);
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vga_bios_size += 8;
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}
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vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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}
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if (is_heathrow) {
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isa_mem_base = 0x80000000;
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/* Register 2 MB of ISA IO space */
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isa_mmio_init(0xfe000000, 0x00200000);
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/* init basic PC hardware */
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pic = heathrow_pic_init(&heathrow_pic_mem_index);
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pci_bus = pci_grackle_init(0xfec00000, pic);
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pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
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ram_size, vga_ram_size,
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vga_bios_offset, vga_bios_size);
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/* XXX: suppress that */
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dummy_irq = i8259_init(NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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if (!nd_table[i].model)
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nd_table[i].model = "ne2k_pci";
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pci_nic_init(pci_bus, &nd_table[i], -1);
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}
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pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
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/* cuda also initialize ADB */
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cuda_mem_index = cuda_init(pic[0x12]);
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adb_kbd_init(&adb_bus);
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adb_mouse_init(&adb_bus);
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{
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MacIONVRAMState *nvr;
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nvr = macio_nvram_init();
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pmac_format_nvram_partition(nvr->data, 0x2000);
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}
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macio_init(pci_bus, 0x0017);
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nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
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arch_name = "HEATHROW";
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} else {
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isa_mem_base = 0x80000000;
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/* Register 8 MB of ISA IO space */
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isa_mmio_init(0xf2000000, 0x00800000);
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/* UniN init */
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unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
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cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
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openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
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openpic_irqs[0] =
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|
qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
|
|
for (i = 0; i < smp_cpus; i++) {
|
|
/* Mac99 IRQ connection between OpenPIC outputs pins
|
|
* and PowerPC input pins
|
|
*/
|
|
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
|
|
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
|
|
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
|
|
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
|
|
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; /* Not connected ? */
|
|
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
|
|
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; /* Check this */
|
|
}
|
|
pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
|
|
openpic_irqs, NULL);
|
|
pci_bus = pci_pmac_init(pic);
|
|
/* init basic PC hardware */
|
|
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
|
|
ram_size, vga_ram_size,
|
|
vga_bios_offset, vga_bios_size);
|
|
|
|
/* XXX: suppress that */
|
|
dummy_irq = i8259_init(NULL);
|
|
|
|
/* XXX: use Mac Serial port */
|
|
serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
|
|
for(i = 0; i < nb_nics; i++) {
|
|
if (!nd_table[i].model)
|
|
nd_table[i].model = "ne2k_pci";
|
|
pci_nic_init(pci_bus, &nd_table[i], -1);
|
|
}
|
|
#if 1
|
|
ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
|
|
ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
|
|
#else
|
|
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
|
|
#endif
|
|
/* cuda also initialize ADB */
|
|
cuda_mem_index = cuda_init(pic[0x19]);
|
|
|
|
adb_kbd_init(&adb_bus);
|
|
adb_mouse_init(&adb_bus);
|
|
|
|
macio_init(pci_bus, 0x0022);
|
|
|
|
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
|
|
|
arch_name = "MAC99";
|
|
}
|
|
|
|
if (usb_enabled) {
|
|
usb_ohci_init_pci(pci_bus, 3, -1);
|
|
}
|
|
|
|
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
|
|
graphic_depth = 15;
|
|
|
|
PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
|
|
kernel_base, kernel_size,
|
|
kernel_cmdline,
|
|
initrd_base, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth);
|
|
/* No PCI init: the BIOS will do it */
|
|
|
|
/* Special port to get debug messages from Open-Firmware */
|
|
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
|
|
}
|
|
|
|
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
|
|
DisplayState *ds, const char **fd_filename,
|
|
int snapshot,
|
|
const char *kernel_filename,
|
|
const char *kernel_cmdline,
|
|
const char *initrd_filename,
|
|
const char *cpu_model)
|
|
{
|
|
ppc_chrp_init(ram_size, vga_ram_size, boot_device,
|
|
ds, fd_filename, snapshot,
|
|
kernel_filename, kernel_cmdline,
|
|
initrd_filename, cpu_model, 0);
|
|
}
|
|
|
|
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
|
|
DisplayState *ds, const char **fd_filename,
|
|
int snapshot,
|
|
const char *kernel_filename,
|
|
const char *kernel_cmdline,
|
|
const char *initrd_filename,
|
|
const char *cpu_model)
|
|
{
|
|
ppc_chrp_init(ram_size, vga_ram_size, boot_device,
|
|
ds, fd_filename, snapshot,
|
|
kernel_filename, kernel_cmdline,
|
|
initrd_filename, cpu_model, 1);
|
|
}
|
|
|
|
QEMUMachine core99_machine = {
|
|
"mac99",
|
|
"Mac99 based PowerMAC",
|
|
ppc_core99_init,
|
|
};
|
|
|
|
QEMUMachine heathrow_machine = {
|
|
"g3bw",
|
|
"Heathrow based PowerMAC",
|
|
ppc_heathrow_init,
|
|
};
|