354 lines
10 KiB
C
354 lines
10 KiB
C
/*
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* QEMU model for the AXIS devboard 88.
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*
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* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "net/net.h"
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#include "hw/block/flash.h"
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#include "hw/boards.h"
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#include "hw/cris/etraxfs.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "boot.h"
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#include "exec/address-spaces.h"
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#include "sysemu/qtest.h"
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#include "sysemu/sysemu.h"
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#define D(x)
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#define DNAND(x)
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struct nand_state_t
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{
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DeviceState *nand;
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MemoryRegion iomem;
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unsigned int rdy:1;
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unsigned int ale:1;
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unsigned int cle:1;
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unsigned int ce:1;
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};
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static struct nand_state_t nand_state;
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static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
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{
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struct nand_state_t *s = opaque;
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uint32_t r;
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int rdy;
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r = nand_getio(s->nand);
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nand_getpins(s->nand, &rdy);
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s->rdy = rdy;
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DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
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return r;
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}
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static void
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nand_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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struct nand_state_t *s = opaque;
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int rdy;
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DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
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nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
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nand_setio(s->nand, value);
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nand_getpins(s->nand, &rdy);
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s->rdy = rdy;
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}
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static const MemoryRegionOps nand_ops = {
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.read = nand_read,
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.write = nand_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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struct tempsensor_t
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{
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unsigned int shiftreg;
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unsigned int count;
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enum {
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ST_OUT, ST_IN, ST_Z
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} state;
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uint16_t regs[3];
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};
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static void tempsensor_clkedge(struct tempsensor_t *s,
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unsigned int clk, unsigned int data_in)
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{
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D(printf("%s clk=%d state=%d sr=%x\n", __func__,
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clk, s->state, s->shiftreg));
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if (s->count == 0) {
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s->count = 16;
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s->state = ST_OUT;
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}
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switch (s->state) {
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case ST_OUT:
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/* Output reg is clocked at negedge. */
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if (!clk) {
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s->count--;
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s->shiftreg <<= 1;
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if (s->count == 0) {
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s->shiftreg = 0;
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s->state = ST_IN;
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s->count = 16;
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}
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}
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break;
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case ST_Z:
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if (clk) {
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s->count--;
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if (s->count == 0) {
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s->shiftreg = 0;
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s->state = ST_OUT;
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s->count = 16;
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}
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}
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break;
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case ST_IN:
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/* Indata is sampled at posedge. */
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if (clk) {
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s->count--;
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s->shiftreg <<= 1;
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s->shiftreg |= data_in & 1;
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if (s->count == 0) {
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D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
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s->regs[0] = s->shiftreg;
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s->state = ST_OUT;
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s->count = 16;
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if ((s->regs[0] & 0xff) == 0) {
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/* 25 degrees celsius. */
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s->shiftreg = 0x0b9f;
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} else if ((s->regs[0] & 0xff) == 0xff) {
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/* Sensor ID, 0x8100 LM70. */
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s->shiftreg = 0x8100;
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} else
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printf("Invalid tempsens state %x\n", s->regs[0]);
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}
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}
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break;
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}
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}
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#define RW_PA_DOUT 0x00
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#define R_PA_DIN 0x01
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#define RW_PA_OE 0x02
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#define RW_PD_DOUT 0x10
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#define R_PD_DIN 0x11
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#define RW_PD_OE 0x12
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static struct gpio_state_t
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{
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MemoryRegion iomem;
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struct nand_state_t *nand;
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struct tempsensor_t tempsensor;
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uint32_t regs[0x5c / 4];
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} gpio_state;
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static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
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{
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struct gpio_state_t *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr)
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{
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case R_PA_DIN:
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r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
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/* Encode pins from the nand. */
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r |= s->nand->rdy << 7;
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break;
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case R_PD_DIN:
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r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
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/* Encode temp sensor pins. */
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r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
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break;
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default:
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r = s->regs[addr];
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break;
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}
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return r;
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D(printf("%s %x=%x\n", __func__, addr, r));
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}
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static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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struct gpio_state_t *s = opaque;
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D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
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addr >>= 2;
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switch (addr)
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{
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case RW_PA_DOUT:
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/* Decode nand pins. */
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s->nand->ale = !!(value & (1 << 6));
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s->nand->cle = !!(value & (1 << 5));
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s->nand->ce = !!(value & (1 << 4));
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s->regs[addr] = value;
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break;
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case RW_PD_DOUT:
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/* Temp sensor clk. */
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if ((s->regs[addr] ^ value) & 2)
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tempsensor_clkedge(&s->tempsensor, !!(value & 2),
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!!(value & 16));
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s->regs[addr] = value;
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break;
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default:
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s->regs[addr] = value;
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break;
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}
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}
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static const MemoryRegionOps gpio_ops = {
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.read = gpio_read,
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.write = gpio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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#define INTMEM_SIZE (128 * KiB)
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static struct cris_load_info li;
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static
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void axisdev88_init(MachineState *machine)
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{
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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CRISCPU *cpu;
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DeviceState *dev;
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SysBusDevice *s;
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DriveInfo *nand;
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qemu_irq irq[30], nmi[2];
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void *etraxfs_dmac;
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struct etraxfs_dma_client *dma_eth;
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int i;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
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/* init CPUs */
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cpu = CRIS_CPU(cpu_create(machine->cpu_type));
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memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram);
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/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
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internal memory. */
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memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
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INTMEM_SIZE, &error_fatal);
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memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
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/* Attach a NAND flash to CS1. */
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nand = drive_get(IF_MTD, 0, 0);
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nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
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NAND_MFR_STMICRO, 0x39);
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memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
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"nand", 0x05000000);
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memory_region_add_subregion(address_space_mem, 0x10000000,
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&nand_state.iomem);
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gpio_state.nand = &nand_state;
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memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
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"gpio", 0x5c);
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memory_region_add_subregion(address_space_mem, 0x3001a000,
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&gpio_state.iomem);
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dev = qdev_new("etraxfs,pic");
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, 0x3001c000);
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
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sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
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for (i = 0; i < 30; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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nmi[0] = qdev_get_gpio_in(dev, 30);
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nmi[1] = qdev_get_gpio_in(dev, 31);
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etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
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for (i = 0; i < 10; i++) {
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/* On ETRAX, odd numbered channels are inputs. */
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etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
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}
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/* Add the two ethernet blocks. */
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dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
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etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
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if (nb_nics > 1) {
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etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
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}
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/* The DMA Connector block is missing, hardwire things for now. */
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etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
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if (nb_nics > 1) {
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etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
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etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
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}
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/* 2 timers. */
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sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
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sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
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for (i = 0; i < 4; i++) {
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etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i));
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}
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if (kernel_filename) {
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li.image_filename = kernel_filename;
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li.cmdline = kernel_cmdline;
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li.ram_size = machine->ram_size;
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cris_load_image(cpu, &li);
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} else if (!qtest_enabled()) {
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fprintf(stderr, "Kernel image must be specified\n");
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exit(1);
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}
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}
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static void axisdev88_machine_init(MachineClass *mc)
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{
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mc->desc = "AXIS devboard 88";
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mc->init = axisdev88_init;
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mc->is_default = true;
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mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32");
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mc->default_ram_id = "axisdev88.ram";
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}
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DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)
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