12fde9bcdb
Add opcodes for backend support for 128-bit memory operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
163 lines
5.4 KiB
C
163 lines
5.4 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef SPARC_TCG_TARGET_H
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#define SPARC_TCG_TARGET_H
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
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#define TCG_TARGET_NB_REGS 32
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#define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB)
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typedef enum {
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TCG_REG_G0 = 0,
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TCG_REG_G1,
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TCG_REG_G2,
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TCG_REG_G3,
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TCG_REG_G4,
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TCG_REG_G5,
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TCG_REG_G6,
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TCG_REG_G7,
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TCG_REG_O0,
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TCG_REG_O1,
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TCG_REG_O2,
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TCG_REG_O3,
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TCG_REG_O4,
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TCG_REG_O5,
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TCG_REG_O6,
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TCG_REG_O7,
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TCG_REG_L0,
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TCG_REG_L1,
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TCG_REG_L2,
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TCG_REG_L3,
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TCG_REG_L4,
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TCG_REG_L5,
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TCG_REG_L6,
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TCG_REG_L7,
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TCG_REG_I0,
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TCG_REG_I1,
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TCG_REG_I2,
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TCG_REG_I3,
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TCG_REG_I4,
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TCG_REG_I5,
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TCG_REG_I6,
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TCG_REG_I7,
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} TCGReg;
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_O6
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#define TCG_TARGET_STACK_BIAS 2047
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#define TCG_TARGET_STACK_ALIGN 16
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#define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS)
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#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND
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#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
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#if defined(__VIS__) && __VIS__ >= 0x300
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#define use_vis3_instructions 1
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#else
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extern bool use_vis3_instructions;
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#endif
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 0
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#define TCG_TARGET_HAS_rot_i32 0
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#define TCG_TARGET_HAS_ext8s_i32 0
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#define TCG_TARGET_HAS_ext16s_i32 0
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#define TCG_TARGET_HAS_ext8u_i32 0
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#define TCG_TARGET_HAS_ext16u_i32 0
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#define TCG_TARGET_HAS_bswap16_i32 0
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#define TCG_TARGET_HAS_bswap32_i32 0
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 0
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_extract_i32 0
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_extrl_i64_i32 1
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#define TCG_TARGET_HAS_extrh_i64_i32 1
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 0
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#define TCG_TARGET_HAS_rot_i64 0
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#define TCG_TARGET_HAS_ext8s_i64 0
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#define TCG_TARGET_HAS_ext16s_i64 0
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 0
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#define TCG_TARGET_HAS_ext16u_i64 0
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 0
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#define TCG_TARGET_HAS_bswap32_i64 0
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#define TCG_TARGET_HAS_bswap64_i64 0
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_clz_i64 0
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_extract_i64 0
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions
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#define TCG_TARGET_HAS_mulsh_i64 0
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_AREG0 TCG_REG_I0
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif
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