qemu/target/riscv/insn_trans
Ivan Klokov bac802ada8 target/riscv: enable 'vstart_eq_zero' in the end of insns
The vstart_eq_zero flag is updated at the beginning of the translation
phase from the env->vstart variable. During the execution phase all
functions will set env->vstart = 0 after a successful execution, but the
vstart_eq_zero flag remains the same as at the start of the block. This
will wrongly cause SIGILLs in translations that requires env->vstart = 0
and might be reading vstart_eq_zero = false.

This patch adds a new finalize_rvv_inst() helper that is called at the
end of each vector instruction that will both update vstart_eq_zero and
do a mark_vs_dirty().

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240314175704.478276-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-22 15:24:37 +10:00
..
trans_privileged.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rva.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv: enable 'vstart_eq_zero' in the end of insns 2024-03-22 15:24:37 +10:00
trans_rvd.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvf.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvi.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvv.c.inc target/riscv: enable 'vstart_eq_zero' in the end of insns 2024-03-22 15:24:37 +10:00
trans_rvvk.c.inc target/riscv: enable 'vstart_eq_zero' in the end of insns 2024-03-22 15:24:37 +10:00
trans_rvzacas.c.inc target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc target/riscv: Update $ra with current $pc in trans_cm_jalt() 2024-03-08 15:37:20 +10:00
trans_rvzfa.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzicbo.c.inc target/riscv: rename ext_icboz to ext_zicboz 2023-11-07 11:02:17 +10:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_xthead.c.inc target/riscv: Enable xtheadsync under user mode 2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00