dfb3630562
These modifiers control, on a per-memory-op basis, whether unaligned memory accesses are allowed. The default setting reflects the target's definition of ALIGNED_ONLY. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
577 lines
21 KiB
C
577 lines
21 KiB
C
/*
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* Software MMU support
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*
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* Generate helpers used by TCG for qemu_ld/st ops and code load
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* functions.
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*
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* Included from target op helpers and exec.c.
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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#include "exec/memory.h"
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#define DATA_SIZE (1 << SHIFT)
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#if DATA_SIZE == 8
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#define SUFFIX q
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#define LSUFFIX q
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#define SDATA_TYPE int64_t
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#define DATA_TYPE uint64_t
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#elif DATA_SIZE == 4
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#define SUFFIX l
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#define LSUFFIX l
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#define SDATA_TYPE int32_t
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#define DATA_TYPE uint32_t
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#elif DATA_SIZE == 2
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#define SUFFIX w
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#define LSUFFIX uw
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#define SDATA_TYPE int16_t
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#define DATA_TYPE uint16_t
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#elif DATA_SIZE == 1
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#define SUFFIX b
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#define LSUFFIX ub
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#define SDATA_TYPE int8_t
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#define DATA_TYPE uint8_t
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#else
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#error unsupported data size
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#endif
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/* For the benefit of TCG generated code, we want to avoid the complication
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of ABI-specific return type promotion and always return a value extended
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to the register size of the host. This is tcg_target_long, except in the
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case of a 32-bit host and 64-bit data, and for that we always have
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uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
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#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
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# define WORD_TYPE DATA_TYPE
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# define USUFFIX SUFFIX
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#else
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# define WORD_TYPE tcg_target_ulong
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# define USUFFIX glue(u, SUFFIX)
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# define SSUFFIX glue(s, SUFFIX)
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#endif
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#ifdef SOFTMMU_CODE_ACCESS
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#define READ_ACCESS_TYPE MMU_INST_FETCH
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#define ADDR_READ addr_code
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#else
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#define READ_ACCESS_TYPE MMU_DATA_LOAD
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#define ADDR_READ addr_read
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#endif
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#if DATA_SIZE == 8
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# define BSWAP(X) bswap64(X)
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#elif DATA_SIZE == 4
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# define BSWAP(X) bswap32(X)
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#elif DATA_SIZE == 2
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# define BSWAP(X) bswap16(X)
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#else
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# define BSWAP(X) (X)
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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# define TGT_BE(X) (X)
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# define TGT_LE(X) BSWAP(X)
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#else
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# define TGT_BE(X) BSWAP(X)
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# define TGT_LE(X) (X)
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#endif
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#if DATA_SIZE == 1
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# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name helper_le_ld_name
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# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name helper_le_lds_name
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# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name helper_le_st_name
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#else
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# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
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# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
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# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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# define helper_te_ld_name helper_be_ld_name
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# define helper_te_st_name helper_be_st_name
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#else
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# define helper_te_ld_name helper_le_ld_name
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# define helper_te_st_name helper_le_st_name
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#endif
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/* macro to check the victim tlb */
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#define VICTIM_TLB_HIT(ty) \
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({ \
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/* we are about to do a page table walk. our last hope is the \
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* victim tlb. try to refill from the victim tlb before walking the \
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* page table. */ \
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int vidx; \
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CPUIOTLBEntry tmpiotlb; \
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CPUTLBEntry tmptlb; \
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for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) { \
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if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
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/* found entry in victim tlb, swap tlb and iotlb */ \
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tmptlb = env->tlb_table[mmu_idx][index]; \
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env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
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env->tlb_v_table[mmu_idx][vidx] = tmptlb; \
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tmpiotlb = env->iotlb[mmu_idx][index]; \
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env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx]; \
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env->iotlb_v[mmu_idx][vidx] = tmpiotlb; \
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break; \
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} \
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} \
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/* return true when there is a vtlb hit, i.e. vidx >=0 */ \
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vidx >= 0; \
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})
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#ifndef SOFTMMU_CODE_ACCESS
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static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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CPUIOTLBEntry *iotlbentry,
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target_ulong addr,
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uintptr_t retaddr)
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{
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uint64_t val;
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CPUState *cpu = ENV_GET_CPU(env);
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hwaddr physaddr = iotlbentry->addr;
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MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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cpu->mem_io_pc = retaddr;
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if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
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cpu_io_recompile(cpu, retaddr);
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}
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cpu->mem_io_vaddr = addr;
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memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT,
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iotlbentry->attrs);
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return val;
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}
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#endif
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#ifdef SOFTMMU_CODE_ACCESS
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static __attribute__((unused))
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#endif
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WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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unsigned mmu_idx = get_mmuidx(oi);
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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uintptr_t haddr;
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DATA_TYPE res;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if ((addr & (DATA_SIZE - 1)) != 0
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&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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if (!VICTIM_TLB_HIT(ADDR_READ)) {
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tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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CPUIOTLBEntry *iotlbentry;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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iotlbentry = &env->iotlb[mmu_idx][index];
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
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res = TGT_LE(res);
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return res;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2;
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unsigned shift;
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do_unaligned_access:
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if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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/* Note the adjustment at the beginning of the function.
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Undo that for the recursion. */
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res1 = helper_le_ld_name(env, addr1, oi, retaddr + GETPC_ADJ);
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res2 = helper_le_ld_name(env, addr2, oi, retaddr + GETPC_ADJ);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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/* Little-endian combine. */
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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return res;
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}
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/* Handle aligned access or unaligned access in the same page. */
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if ((addr & (DATA_SIZE - 1)) != 0
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&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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#if DATA_SIZE == 1
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res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
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#else
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res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
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#endif
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return res;
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}
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#if DATA_SIZE > 1
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#ifdef SOFTMMU_CODE_ACCESS
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static __attribute__((unused))
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#endif
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WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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unsigned mmu_idx = get_mmuidx(oi);
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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uintptr_t haddr;
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DATA_TYPE res;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if ((addr & (DATA_SIZE - 1)) != 0
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&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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if (!VICTIM_TLB_HIT(ADDR_READ)) {
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tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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CPUIOTLBEntry *iotlbentry;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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iotlbentry = &env->iotlb[mmu_idx][index];
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
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res = TGT_BE(res);
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return res;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2;
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unsigned shift;
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do_unaligned_access:
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if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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/* Note the adjustment at the beginning of the function.
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Undo that for the recursion. */
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res1 = helper_be_ld_name(env, addr1, oi, retaddr + GETPC_ADJ);
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res2 = helper_be_ld_name(env, addr2, oi, retaddr + GETPC_ADJ);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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/* Big-endian combine. */
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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return res;
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}
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/* Handle aligned access or unaligned access in the same page. */
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if ((addr & (DATA_SIZE - 1)) != 0
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&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
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return res;
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}
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#endif /* DATA_SIZE > 1 */
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DATA_TYPE
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glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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int mmu_idx)
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{
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TCGMemOpIdx oi = make_memop_idx(SHIFT, mmu_idx);
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return helper_te_ld_name (env, addr, oi, GETRA());
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}
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#ifndef SOFTMMU_CODE_ACCESS
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/* Provide signed versions of the load routines as well. We can of course
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avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
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#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
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WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
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}
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# if DATA_SIZE > 1
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WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
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}
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# endif
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#endif
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static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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CPUIOTLBEntry *iotlbentry,
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DATA_TYPE val,
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target_ulong addr,
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uintptr_t retaddr)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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hwaddr physaddr = iotlbentry->addr;
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MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
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physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
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if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
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cpu_io_recompile(cpu, retaddr);
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}
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cpu->mem_io_vaddr = addr;
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cpu->mem_io_pc = retaddr;
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memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT,
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iotlbentry->attrs);
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}
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void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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unsigned mmu_idx = get_mmuidx(oi);
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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uintptr_t haddr;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if ((addr & (DATA_SIZE - 1)) != 0
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&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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if (!VICTIM_TLB_HIT(addr_write)) {
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tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
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}
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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CPUIOTLBEntry *iotlbentry;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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iotlbentry = &env->iotlb[mmu_idx][index];
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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val = TGT_LE(val);
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glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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int i;
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do_unaligned_access:
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if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
|
|
}
|
|
/* XXX: not efficient, but simple */
|
|
/* Note: relies on the fact that tlb_fill() does not remove the
|
|
* previous page from the TLB cache. */
|
|
for (i = DATA_SIZE - 1; i >= 0; i--) {
|
|
/* Little-endian extract. */
|
|
uint8_t val8 = val >> (i * 8);
|
|
/* Note the adjustment at the beginning of the function.
|
|
Undo that for the recursion. */
|
|
glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
|
|
oi, retaddr + GETPC_ADJ);
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Handle aligned access or unaligned access in the same page. */
|
|
if ((addr & (DATA_SIZE - 1)) != 0
|
|
&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
|
|
haddr = addr + env->tlb_table[mmu_idx][index].addend;
|
|
#if DATA_SIZE == 1
|
|
glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
|
|
#else
|
|
glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
|
|
#endif
|
|
}
|
|
|
|
#if DATA_SIZE > 1
|
|
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
|
|
TCGMemOpIdx oi, uintptr_t retaddr)
|
|
{
|
|
unsigned mmu_idx = get_mmuidx(oi);
|
|
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
|
|
uintptr_t haddr;
|
|
|
|
/* Adjust the given return address. */
|
|
retaddr -= GETPC_ADJ;
|
|
|
|
/* If the TLB entry is for a different page, reload and try again. */
|
|
if ((addr & TARGET_PAGE_MASK)
|
|
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
|
if ((addr & (DATA_SIZE - 1)) != 0
|
|
&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
if (!VICTIM_TLB_HIT(addr_write)) {
|
|
tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
|
|
}
|
|
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
|
|
}
|
|
|
|
/* Handle an IO access. */
|
|
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
|
CPUIOTLBEntry *iotlbentry;
|
|
if ((addr & (DATA_SIZE - 1)) != 0) {
|
|
goto do_unaligned_access;
|
|
}
|
|
iotlbentry = &env->iotlb[mmu_idx][index];
|
|
|
|
/* ??? Note that the io helpers always read data in the target
|
|
byte ordering. We should push the LE/BE request down into io. */
|
|
val = TGT_BE(val);
|
|
glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
|
|
return;
|
|
}
|
|
|
|
/* Handle slow unaligned access (it spans two pages or IO). */
|
|
if (DATA_SIZE > 1
|
|
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
|
>= TARGET_PAGE_SIZE)) {
|
|
int i;
|
|
do_unaligned_access:
|
|
if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
/* XXX: not efficient, but simple */
|
|
/* Note: relies on the fact that tlb_fill() does not remove the
|
|
* previous page from the TLB cache. */
|
|
for (i = DATA_SIZE - 1; i >= 0; i--) {
|
|
/* Big-endian extract. */
|
|
uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
|
|
/* Note the adjustment at the beginning of the function.
|
|
Undo that for the recursion. */
|
|
glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
|
|
oi, retaddr + GETPC_ADJ);
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Handle aligned access or unaligned access in the same page. */
|
|
if ((addr & (DATA_SIZE - 1)) != 0
|
|
&& (get_memop(oi) & MO_AMASK) == MO_ALIGN) {
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
mmu_idx, retaddr);
|
|
}
|
|
|
|
haddr = addr + env->tlb_table[mmu_idx][index].addend;
|
|
glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
|
|
}
|
|
#endif /* DATA_SIZE > 1 */
|
|
|
|
void
|
|
glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
|
|
DATA_TYPE val, int mmu_idx)
|
|
{
|
|
TCGMemOpIdx oi = make_memop_idx(SHIFT, mmu_idx);
|
|
helper_te_st_name(env, addr, val, oi, GETRA());
|
|
}
|
|
|
|
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
|
|
|
|
#undef READ_ACCESS_TYPE
|
|
#undef SHIFT
|
|
#undef DATA_TYPE
|
|
#undef SUFFIX
|
|
#undef LSUFFIX
|
|
#undef DATA_SIZE
|
|
#undef ADDR_READ
|
|
#undef WORD_TYPE
|
|
#undef SDATA_TYPE
|
|
#undef USUFFIX
|
|
#undef SSUFFIX
|
|
#undef BSWAP
|
|
#undef TGT_BE
|
|
#undef TGT_LE
|
|
#undef CPU_BE
|
|
#undef CPU_LE
|
|
#undef helper_le_ld_name
|
|
#undef helper_be_ld_name
|
|
#undef helper_le_lds_name
|
|
#undef helper_be_lds_name
|
|
#undef helper_le_st_name
|
|
#undef helper_be_st_name
|
|
#undef helper_te_ld_name
|
|
#undef helper_te_st_name
|