e29c7db19d
This model is a top level integration wrapper for hcd-dwc3 and versal-usb2-ctrl-regs modules, this is used by xilinx versal soc's and future xilinx usb subsystems would also be part of it. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1607023357-5096-4-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
/*
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* QEMU model of the Xilinx usb subsystem
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*
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* Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu <sai.pava.boddu@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qom/object.h"
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#include "qapi/error.h"
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#include "hw/qdev-properties.h"
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#include "hw/usb/xlnx-usb-subsystem.h"
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static void versal_usb2_realize(DeviceState *dev, Error **errp)
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{
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VersalUsb2 *s = VERSAL_USB2(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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Error *err = NULL;
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sysbus_realize(SYS_BUS_DEVICE(&s->dwc3), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_realize(SYS_BUS_DEVICE(&s->usb2Ctrl), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_init_mmio(sbd, &s->dwc3_mr);
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sysbus_init_mmio(sbd, &s->usb2Ctrl_mr);
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qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_IRQ);
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}
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static void versal_usb2_init(Object *obj)
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{
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VersalUsb2 *s = VERSAL_USB2(obj);
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object_initialize_child(obj, "versal.dwc3", &s->dwc3,
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TYPE_USB_DWC3);
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object_initialize_child(obj, "versal.usb2-ctrl", &s->usb2Ctrl,
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TYPE_XILINX_VERSAL_USB2_CTRL_REGS);
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memory_region_init_alias(&s->dwc3_mr, obj, "versal.dwc3_alias",
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&s->dwc3.iomem, 0, DWC3_SIZE);
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memory_region_init_alias(&s->usb2Ctrl_mr, obj, "versal.usb2Ctrl_alias",
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&s->usb2Ctrl.iomem, 0, USB2_REGS_R_MAX * 4);
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qdev_alias_all_properties(DEVICE(&s->dwc3), obj);
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qdev_alias_all_properties(DEVICE(&s->dwc3.sysbus_xhci), obj);
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object_property_add_alias(obj, "dma", OBJECT(&s->dwc3.sysbus_xhci), "dma");
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}
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static void versal_usb2_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = versal_usb2_realize;
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}
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static const TypeInfo versal_usb2_info = {
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.name = TYPE_XILINX_VERSAL_USB2,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(VersalUsb2),
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.class_init = versal_usb2_class_init,
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.instance_init = versal_usb2_init,
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};
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static void versal_usb_types(void)
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{
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type_register_static(&versal_usb2_info);
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}
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type_init(versal_usb_types)
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