db1015e92e
Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName"
declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
$(git grep -l '' -- '*.[ch]')
which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
282 lines
8.7 KiB
C
282 lines
8.7 KiB
C
/*
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* i.MX FEC/ENET Ethernet Controller emulation.
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*
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* Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
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*
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* Based on Coldfire Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef IMX_FEC_H
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#define IMX_FEC_H
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#include "qom/object.h"
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#define TYPE_IMX_FEC "imx.fec"
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typedef struct IMXFECState IMXFECState;
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#define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC)
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#define TYPE_IMX_ENET "imx.enet"
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#include "hw/sysbus.h"
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#include "net/net.h"
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#define ENET_EIR 1
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#define ENET_EIMR 2
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#define ENET_RDAR 4
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#define ENET_TDAR 5
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#define ENET_ECR 9
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#define ENET_MMFR 16
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#define ENET_MSCR 17
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#define ENET_MIBC 25
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#define ENET_RCR 33
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#define ENET_TCR 49
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#define ENET_PALR 57
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#define ENET_PAUR 58
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#define ENET_OPD 59
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#define ENET_IAUR 70
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#define ENET_IALR 71
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#define ENET_GAUR 72
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#define ENET_GALR 73
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#define ENET_TFWR 81
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#define ENET_FRBR 83
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#define ENET_FRSR 84
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#define ENET_TDSR1 89
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#define ENET_TDSR2 92
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#define ENET_RDSR 96
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#define ENET_TDSR 97
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#define ENET_MRBR 98
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#define ENET_RSFL 100
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#define ENET_RSEM 101
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#define ENET_RAEM 102
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#define ENET_RAFL 103
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#define ENET_TSEM 104
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#define ENET_TAEM 105
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#define ENET_TAFL 106
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#define ENET_TIPG 107
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#define ENET_FTRL 108
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#define ENET_TACC 112
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#define ENET_RACC 113
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#define ENET_TDAR1 121
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#define ENET_TDAR2 123
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#define ENET_MIIGSK_CFGR 192
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#define ENET_MIIGSK_ENR 194
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#define ENET_ATCR 256
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#define ENET_ATVR 257
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#define ENET_ATOFF 258
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#define ENET_ATPER 259
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#define ENET_ATCOR 260
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#define ENET_ATINC 261
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#define ENET_ATSTMP 262
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#define ENET_TGSR 385
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#define ENET_TCSR0 386
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#define ENET_TCCR0 387
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#define ENET_TCSR1 388
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#define ENET_TCCR1 389
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#define ENET_TCSR2 390
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#define ENET_TCCR2 391
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#define ENET_TCSR3 392
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#define ENET_TCCR3 393
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#define ENET_MAX 400
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/* EIR and EIMR */
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#define ENET_INT_HB (1 << 31)
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#define ENET_INT_BABR (1 << 30)
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#define ENET_INT_BABT (1 << 29)
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#define ENET_INT_GRA (1 << 28)
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#define ENET_INT_TXF (1 << 27)
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#define ENET_INT_TXB (1 << 26)
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#define ENET_INT_RXF (1 << 25)
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#define ENET_INT_RXB (1 << 24)
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#define ENET_INT_MII (1 << 23)
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#define ENET_INT_EBERR (1 << 22)
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#define ENET_INT_LC (1 << 21)
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#define ENET_INT_RL (1 << 20)
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#define ENET_INT_UN (1 << 19)
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#define ENET_INT_PLR (1 << 18)
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#define ENET_INT_WAKEUP (1 << 17)
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#define ENET_INT_TS_AVAIL (1 << 16)
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#define ENET_INT_TS_TIMER (1 << 15)
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#define ENET_INT_TXF2 (1 << 7)
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#define ENET_INT_TXB2 (1 << 6)
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#define ENET_INT_TXF1 (1 << 3)
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#define ENET_INT_TXB1 (1 << 2)
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#define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
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ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
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ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
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ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
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ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
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ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
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ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)
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/* RDAR */
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#define ENET_RDAR_RDAR (1 << 24)
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/* TDAR */
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#define ENET_TDAR_TDAR (1 << 24)
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/* ECR */
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#define ENET_ECR_RESET (1 << 0)
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#define ENET_ECR_ETHEREN (1 << 1)
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#define ENET_ECR_MAGICEN (1 << 2)
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#define ENET_ECR_SLEEP (1 << 3)
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#define ENET_ECR_EN1588 (1 << 4)
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#define ENET_ECR_SPEED (1 << 5)
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#define ENET_ECR_DBGEN (1 << 6)
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#define ENET_ECR_STOPEN (1 << 7)
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#define ENET_ECR_DSBWP (1 << 8)
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/* MIBC */
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#define ENET_MIBC_MIB_DIS (1 << 31)
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#define ENET_MIBC_MIB_IDLE (1 << 30)
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#define ENET_MIBC_MIB_CLEAR (1 << 29)
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/* RCR */
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#define ENET_RCR_LOOP (1 << 0)
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#define ENET_RCR_DRT (1 << 1)
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#define ENET_RCR_MII_MODE (1 << 2)
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#define ENET_RCR_PROM (1 << 3)
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#define ENET_RCR_BC_REJ (1 << 4)
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#define ENET_RCR_FCE (1 << 5)
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#define ENET_RCR_RGMII_EN (1 << 6)
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#define ENET_RCR_RMII_MODE (1 << 8)
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#define ENET_RCR_RMII_10T (1 << 9)
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#define ENET_RCR_PADEN (1 << 12)
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#define ENET_RCR_PAUFWD (1 << 13)
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#define ENET_RCR_CRCFWD (1 << 14)
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#define ENET_RCR_CFEN (1 << 15)
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#define ENET_RCR_MAX_FL_SHIFT (16)
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#define ENET_RCR_MAX_FL_LENGTH (14)
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#define ENET_RCR_NLC (1 << 30)
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#define ENET_RCR_GRS (1 << 31)
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#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
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/* TCR */
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#define ENET_TCR_GTS (1 << 0)
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#define ENET_TCR_FDEN (1 << 2)
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#define ENET_TCR_TFC_PAUSE (1 << 3)
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#define ENET_TCR_RFC_PAUSE (1 << 4)
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#define ENET_TCR_ADDSEL_SHIFT (5)
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#define ENET_TCR_ADDSEL_LENGTH (3)
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#define ENET_TCR_CRCFWD (1 << 9)
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/* RDSR */
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#define ENET_TWFR_TFWR_SHIFT (0)
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#define ENET_TWFR_TFWR_LENGTH (6)
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#define ENET_TWFR_STRFWD (1 << 8)
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#define ENET_RACC_SHIFT16 BIT(7)
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/* Buffer Descriptor. */
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typedef struct {
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uint16_t length;
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uint16_t flags;
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uint32_t data;
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} IMXFECBufDesc;
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#define ENET_BD_R (1 << 15)
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#define ENET_BD_E (1 << 15)
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#define ENET_BD_O1 (1 << 14)
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#define ENET_BD_W (1 << 13)
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#define ENET_BD_O2 (1 << 12)
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#define ENET_BD_L (1 << 11)
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#define ENET_BD_TC (1 << 10)
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#define ENET_BD_ABC (1 << 9)
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#define ENET_BD_M (1 << 8)
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#define ENET_BD_BC (1 << 7)
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#define ENET_BD_MC (1 << 6)
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#define ENET_BD_LG (1 << 5)
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#define ENET_BD_NO (1 << 4)
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#define ENET_BD_CR (1 << 2)
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#define ENET_BD_OV (1 << 1)
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#define ENET_BD_TR (1 << 0)
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typedef struct {
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uint16_t length;
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uint16_t flags;
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uint32_t data;
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uint16_t status;
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uint16_t option;
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uint16_t checksum;
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uint16_t head_proto;
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uint32_t last_buffer;
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uint32_t timestamp;
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uint32_t reserved[2];
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} IMXENETBufDesc;
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#define ENET_BD_ME (1 << 15)
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#define ENET_BD_TX_INT (1 << 14)
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#define ENET_BD_TS (1 << 13)
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#define ENET_BD_PINS (1 << 12)
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#define ENET_BD_IINS (1 << 11)
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#define ENET_BD_PE (1 << 10)
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#define ENET_BD_CE (1 << 9)
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#define ENET_BD_UC (1 << 8)
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#define ENET_BD_RX_INT (1 << 7)
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#define ENET_BD_TXE (1 << 15)
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#define ENET_BD_UE (1 << 13)
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#define ENET_BD_EE (1 << 12)
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#define ENET_BD_FE (1 << 11)
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#define ENET_BD_LCE (1 << 10)
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#define ENET_BD_OE (1 << 9)
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#define ENET_BD_TSE (1 << 8)
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#define ENET_BD_ICE (1 << 5)
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#define ENET_BD_PCR (1 << 4)
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#define ENET_BD_VLAN (1 << 2)
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#define ENET_BD_IPV6 (1 << 1)
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#define ENET_BD_FRAG (1 << 0)
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#define ENET_BD_BDU (1 << 31)
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#define ENET_TX_RING_NUM 3
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#define FSL_IMX25_FEC_SIZE 0x4000
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struct IMXFECState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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NICState *nic;
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NICConf conf;
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qemu_irq irq[2];
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MemoryRegion iomem;
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uint32_t regs[ENET_MAX];
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uint32_t rx_descriptor;
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uint32_t tx_descriptor[ENET_TX_RING_NUM];
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uint32_t tx_ring_num;
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uint32_t phy_status;
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uint32_t phy_control;
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uint32_t phy_advertise;
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uint32_t phy_int;
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uint32_t phy_int_mask;
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uint32_t phy_num;
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bool is_fec;
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/* Buffer used to assemble a Tx frame */
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uint8_t frame[ENET_MAX_FRAME_SIZE];
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};
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#endif
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