db1015e92e
Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName"
declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
$(git grep -l '' -- '*.[ch]')
which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
662 lines
17 KiB
C
662 lines
17 KiB
C
/*
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* Arm PrimeCell PL041 Advanced Audio Codec Interface
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*
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* Copyright (c) 2011
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* Written by Mathieu Sonet - www.elasticsheep.com
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*
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* This code is licensed under the GPL.
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*
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* *****************************************************************
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*
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* This driver emulates the ARM AACI interface
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* connected to a LM4549 codec.
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*
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* Limitations:
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* - Supports only a playback on one channel (Versatile/Vexpress)
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* - Supports only one TX FIFO in compact-mode or non-compact mode.
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* - Supports playback of 12, 16, 18 and 20 bits samples.
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* - Record is not supported.
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* - The PL041 is hardwired to a LM4549 codec.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "pl041.h"
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#include "lm4549.h"
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#include "migration/vmstate.h"
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#include "qom/object.h"
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#if 0
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#define PL041_DEBUG_LEVEL 1
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#endif
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#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 1)
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#define DBG_L1(fmt, ...) \
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do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DBG_L1(fmt, ...) \
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do { } while (0)
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#endif
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#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 2)
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#define DBG_L2(fmt, ...) \
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do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DBG_L2(fmt, ...) \
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do { } while (0)
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#endif
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#define MAX_FIFO_DEPTH (1024)
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#define DEFAULT_FIFO_DEPTH (8)
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#define SLOT1_RW (1 << 19)
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/* This FIFO only stores 20-bit samples on 32-bit words.
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So its level is independent of the selected mode */
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typedef struct {
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uint32_t level;
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uint32_t data[MAX_FIFO_DEPTH];
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} pl041_fifo;
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typedef struct {
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pl041_fifo tx_fifo;
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uint8_t tx_enabled;
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uint8_t tx_compact_mode;
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uint8_t tx_sample_size;
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pl041_fifo rx_fifo;
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uint8_t rx_enabled;
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uint8_t rx_compact_mode;
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uint8_t rx_sample_size;
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} pl041_channel;
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#define TYPE_PL041 "pl041"
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typedef struct PL041State PL041State;
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#define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041)
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struct PL041State {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t fifo_depth; /* FIFO depth in non-compact mode */
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pl041_regfile regs;
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pl041_channel fifo1;
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lm4549_state codec;
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};
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static const unsigned char pl041_default_id[8] = {
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0x41, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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#if defined(PL041_DEBUG_LEVEL)
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#define REGISTER(name, offset) #name,
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static const char *pl041_regs_name[] = {
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#include "pl041.hx"
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};
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#undef REGISTER
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#endif
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#if defined(PL041_DEBUG_LEVEL)
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static const char *get_reg_name(hwaddr offset)
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{
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if (offset <= PL041_dr1_7) {
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return pl041_regs_name[offset >> 2];
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}
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return "unknown";
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}
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#endif
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static uint8_t pl041_compute_periphid3(PL041State *s)
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{
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uint8_t id3 = 1; /* One channel */
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/* Add the fifo depth information */
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switch (s->fifo_depth) {
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case 8:
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id3 |= 0 << 3;
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break;
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case 32:
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id3 |= 1 << 3;
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break;
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case 64:
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id3 |= 2 << 3;
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break;
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case 128:
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id3 |= 3 << 3;
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break;
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case 256:
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id3 |= 4 << 3;
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break;
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case 512:
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id3 |= 5 << 3;
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break;
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case 1024:
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id3 |= 6 << 3;
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break;
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case 2048:
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id3 |= 7 << 3;
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break;
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}
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return id3;
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}
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static void pl041_reset(PL041State *s)
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{
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DBG_L1("pl041_reset\n");
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memset(&s->regs, 0x00, sizeof(pl041_regfile));
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s->regs.slfr = SL1TXEMPTY | SL2TXEMPTY | SL12TXEMPTY;
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s->regs.sr1 = TXFE | RXFE | TXHE;
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s->regs.isr1 = 0;
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memset(&s->fifo1, 0x00, sizeof(s->fifo1));
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}
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static void pl041_fifo1_write(PL041State *s, uint32_t value)
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{
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pl041_channel *channel = &s->fifo1;
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pl041_fifo *fifo = &s->fifo1.tx_fifo;
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/* Push the value in the FIFO */
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if (channel->tx_compact_mode == 0) {
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/* Non-compact mode */
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if (fifo->level < s->fifo_depth) {
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/* Pad the value with 0 to obtain a 20-bit sample */
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switch (channel->tx_sample_size) {
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case 12:
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value = (value << 8) & 0xFFFFF;
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break;
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case 16:
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value = (value << 4) & 0xFFFFF;
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break;
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case 18:
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value = (value << 2) & 0xFFFFF;
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break;
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case 20:
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default:
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break;
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}
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/* Store the sample in the FIFO */
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fifo->data[fifo->level++] = value;
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}
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#if defined(PL041_DEBUG_LEVEL)
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else {
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DBG_L1("fifo1 write: overrun\n");
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}
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#endif
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} else {
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/* Compact mode */
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if ((fifo->level + 2) < s->fifo_depth) {
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uint32_t i = 0;
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uint32_t sample = 0;
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for (i = 0; i < 2; i++) {
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sample = value & 0xFFFF;
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value = value >> 16;
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/* Pad each sample with 0 to obtain a 20-bit sample */
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switch (channel->tx_sample_size) {
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case 12:
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sample = sample << 8;
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break;
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case 16:
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default:
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sample = sample << 4;
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break;
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}
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/* Store the sample in the FIFO */
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fifo->data[fifo->level++] = sample;
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}
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}
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#if defined(PL041_DEBUG_LEVEL)
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else {
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DBG_L1("fifo1 write: overrun\n");
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}
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#endif
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}
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/* Update the status register */
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if (fifo->level > 0) {
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s->regs.sr1 &= ~(TXUNDERRUN | TXFE);
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}
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if (fifo->level >= (s->fifo_depth / 2)) {
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s->regs.sr1 &= ~TXHE;
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}
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if (fifo->level >= s->fifo_depth) {
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s->regs.sr1 |= TXFF;
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}
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DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
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}
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static void pl041_fifo1_transmit(PL041State *s)
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{
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pl041_channel *channel = &s->fifo1;
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pl041_fifo *fifo = &s->fifo1.tx_fifo;
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uint32_t slots = s->regs.txcr1 & TXSLOT_MASK;
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uint32_t written_samples;
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/* Check if FIFO1 transmit is enabled */
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if ((channel->tx_enabled) && (slots & (TXSLOT3 | TXSLOT4))) {
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if (fifo->level >= (s->fifo_depth / 2)) {
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int i;
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DBG_L1("Transfer FIFO level = %i\n", fifo->level);
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/* Try to transfer the whole FIFO */
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for (i = 0; i < (fifo->level / 2); i++) {
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uint32_t left = fifo->data[i * 2];
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uint32_t right = fifo->data[i * 2 + 1];
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/* Transmit two 20-bit samples to the codec */
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if (lm4549_write_samples(&s->codec, left, right) == 0) {
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DBG_L1("Codec buffer full\n");
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break;
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}
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}
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written_samples = i * 2;
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if (written_samples > 0) {
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/* Update the FIFO level */
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fifo->level -= written_samples;
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/* Move back the pending samples to the start of the FIFO */
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for (i = 0; i < fifo->level; i++) {
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fifo->data[i] = fifo->data[written_samples + i];
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}
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/* Update the status register */
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s->regs.sr1 &= ~TXFF;
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if (fifo->level <= (s->fifo_depth / 2)) {
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s->regs.sr1 |= TXHE;
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}
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if (fifo->level == 0) {
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s->regs.sr1 |= TXFE | TXUNDERRUN;
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DBG_L1("Empty FIFO\n");
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}
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}
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}
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}
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}
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static void pl041_isr1_update(PL041State *s)
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{
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/* Update ISR1 */
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if (s->regs.sr1 & TXUNDERRUN) {
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s->regs.isr1 |= URINTR;
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} else {
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s->regs.isr1 &= ~URINTR;
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}
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if (s->regs.sr1 & TXHE) {
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s->regs.isr1 |= TXINTR;
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} else {
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s->regs.isr1 &= ~TXINTR;
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}
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if (!(s->regs.sr1 & TXBUSY) && (s->regs.sr1 & TXFE)) {
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s->regs.isr1 |= TXCINTR;
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} else {
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s->regs.isr1 &= ~TXCINTR;
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}
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/* Update the irq state */
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qemu_set_irq(s->irq, ((s->regs.isr1 & s->regs.ie1) > 0) ? 1 : 0);
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DBG_L2("Set interrupt sr1 = 0x%08x isr1 = 0x%08x masked = 0x%08x\n",
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s->regs.sr1, s->regs.isr1, s->regs.isr1 & s->regs.ie1);
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}
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static void pl041_request_data(void *opaque)
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{
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PL041State *s = (PL041State *)opaque;
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/* Trigger pending transfers */
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pl041_fifo1_transmit(s);
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pl041_isr1_update(s);
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}
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static uint64_t pl041_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PL041State *s = (PL041State *)opaque;
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int value;
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if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
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if (offset == PL041_periphid3) {
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value = pl041_compute_periphid3(s);
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} else {
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value = pl041_default_id[(offset - PL041_periphid0) >> 2];
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}
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DBG_L1("pl041_read [0x%08x] => 0x%08x\n", offset, value);
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return value;
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} else if (offset <= PL041_dr4_7) {
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value = *((uint32_t *)&s->regs + (offset >> 2));
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} else {
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DBG_L1("pl041_read: Reserved offset %x\n", (int)offset);
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return 0;
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}
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switch (offset) {
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case PL041_allints:
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value = s->regs.isr1 & 0x7F;
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break;
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}
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DBG_L1("pl041_read [0x%08x] %s => 0x%08x\n", offset,
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get_reg_name(offset), value);
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return value;
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}
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static void pl041_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PL041State *s = (PL041State *)opaque;
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uint16_t control, data;
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uint32_t result;
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DBG_L1("pl041_write [0x%08x] %s <= 0x%08x\n", offset,
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get_reg_name(offset), (unsigned int)value);
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/* Write the register */
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if (offset <= PL041_dr4_7) {
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*((uint32_t *)&s->regs + (offset >> 2)) = value;
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} else {
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DBG_L1("pl041_write: Reserved offset %x\n", (int)offset);
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return;
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}
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/* Execute the actions */
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switch (offset) {
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case PL041_txcr1:
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{
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pl041_channel *channel = &s->fifo1;
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uint32_t txen = s->regs.txcr1 & TXEN;
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uint32_t tsize = (s->regs.txcr1 & TSIZE_MASK) >> TSIZE_MASK_BIT;
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uint32_t compact_mode = (s->regs.txcr1 & TXCOMPACT) ? 1 : 0;
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#if defined(PL041_DEBUG_LEVEL)
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uint32_t slots = (s->regs.txcr1 & TXSLOT_MASK) >> TXSLOT_MASK_BIT;
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uint32_t txfen = (s->regs.txcr1 & TXFEN) > 0 ? 1 : 0;
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#endif
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DBG_L1("=> txen = %i slots = 0x%01x tsize = %i compact = %i "
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"txfen = %i\n", txen, slots, tsize, compact_mode, txfen);
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channel->tx_enabled = txen;
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channel->tx_compact_mode = compact_mode;
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switch (tsize) {
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case 0:
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channel->tx_sample_size = 16;
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break;
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case 1:
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channel->tx_sample_size = 18;
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break;
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case 2:
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channel->tx_sample_size = 20;
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break;
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case 3:
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channel->tx_sample_size = 12;
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break;
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}
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DBG_L1("TX enabled = %i\n", channel->tx_enabled);
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DBG_L1("TX compact mode = %i\n", channel->tx_compact_mode);
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DBG_L1("TX sample width = %i\n", channel->tx_sample_size);
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/* Check if compact mode is allowed with selected tsize */
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if (channel->tx_compact_mode == 1) {
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if ((channel->tx_sample_size == 18) ||
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(channel->tx_sample_size == 20)) {
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channel->tx_compact_mode = 0;
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DBG_L1("Compact mode not allowed with 18/20-bit sample size\n");
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}
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}
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break;
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}
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case PL041_sl1tx:
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s->regs.slfr &= ~SL1TXEMPTY;
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control = (s->regs.sl1tx >> 12) & 0x7F;
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data = (s->regs.sl2tx >> 4) & 0xFFFF;
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if ((s->regs.sl1tx & SLOT1_RW) == 0) {
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/* Write operation */
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lm4549_write(&s->codec, control, data);
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} else {
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/* Read operation */
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result = lm4549_read(&s->codec, control);
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/* Store the returned value */
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s->regs.sl1rx = s->regs.sl1tx & ~SLOT1_RW;
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s->regs.sl2rx = result << 4;
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s->regs.slfr &= ~(SL1RXBUSY | SL2RXBUSY);
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s->regs.slfr |= SL1RXVALID | SL2RXVALID;
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}
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break;
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case PL041_sl2tx:
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s->regs.sl2tx = value;
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s->regs.slfr &= ~SL2TXEMPTY;
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break;
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case PL041_intclr:
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DBG_L1("=> Clear interrupt intclr = 0x%08x isr1 = 0x%08x\n",
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s->regs.intclr, s->regs.isr1);
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if (s->regs.intclr & TXUEC1) {
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s->regs.sr1 &= ~TXUNDERRUN;
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}
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break;
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case PL041_maincr:
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{
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#if defined(PL041_DEBUG_LEVEL)
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char debug[] = " AACIFE SL1RXEN SL1TXEN";
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if (!(value & AACIFE)) {
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debug[0] = '!';
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}
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if (!(value & SL1RXEN)) {
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debug[8] = '!';
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}
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if (!(value & SL1TXEN)) {
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debug[17] = '!';
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}
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DBG_L1("%s\n", debug);
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#endif
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if ((s->regs.maincr & AACIFE) == 0) {
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pl041_reset(s);
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}
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break;
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}
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case PL041_dr1_0:
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case PL041_dr1_1:
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case PL041_dr1_2:
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case PL041_dr1_3:
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pl041_fifo1_write(s, value);
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break;
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}
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/* Transmit the FIFO content */
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pl041_fifo1_transmit(s);
|
|
|
|
/* Update the ISR1 register */
|
|
pl041_isr1_update(s);
|
|
}
|
|
|
|
static void pl041_device_reset(DeviceState *d)
|
|
{
|
|
PL041State *s = PL041(d);
|
|
|
|
pl041_reset(s);
|
|
}
|
|
|
|
static const MemoryRegionOps pl041_ops = {
|
|
.read = pl041_read,
|
|
.write = pl041_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void pl041_init(Object *obj)
|
|
{
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
PL041State *s = PL041(dev);
|
|
|
|
DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
|
|
|
|
/* Connect the device to the sysbus */
|
|
memory_region_init_io(&s->iomem, obj, &pl041_ops, s, "pl041", 0x1000);
|
|
sysbus_init_mmio(dev, &s->iomem);
|
|
sysbus_init_irq(dev, &s->irq);
|
|
}
|
|
|
|
static void pl041_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PL041State *s = PL041(dev);
|
|
|
|
/* Check the device properties */
|
|
switch (s->fifo_depth) {
|
|
case 8:
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
case 256:
|
|
case 512:
|
|
case 1024:
|
|
case 2048:
|
|
break;
|
|
case 16:
|
|
default:
|
|
/* NC FIFO depth of 16 is not allowed because its id bits in
|
|
AACIPERIPHID3 overlap with the id for the default NC FIFO depth */
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"pl041: unsupported non-compact fifo depth [%i]\n",
|
|
s->fifo_depth);
|
|
}
|
|
|
|
/* Init the codec */
|
|
lm4549_init(&s->codec, &pl041_request_data, (void *)s);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_pl041_regfile = {
|
|
.name = "pl041_regfile",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
#define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile),
|
|
#include "pl041.hx"
|
|
#undef REGISTER
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_pl041_fifo = {
|
|
.name = "pl041_fifo",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(level, pl041_fifo),
|
|
VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_pl041_channel = {
|
|
.name = "pl041_channel",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT(tx_fifo, pl041_channel, 0,
|
|
vmstate_pl041_fifo, pl041_fifo),
|
|
VMSTATE_UINT8(tx_enabled, pl041_channel),
|
|
VMSTATE_UINT8(tx_compact_mode, pl041_channel),
|
|
VMSTATE_UINT8(tx_sample_size, pl041_channel),
|
|
VMSTATE_STRUCT(rx_fifo, pl041_channel, 0,
|
|
vmstate_pl041_fifo, pl041_fifo),
|
|
VMSTATE_UINT8(rx_enabled, pl041_channel),
|
|
VMSTATE_UINT8(rx_compact_mode, pl041_channel),
|
|
VMSTATE_UINT8(rx_sample_size, pl041_channel),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_pl041 = {
|
|
.name = "pl041",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(fifo_depth, PL041State),
|
|
VMSTATE_STRUCT(regs, PL041State, 0,
|
|
vmstate_pl041_regfile, pl041_regfile),
|
|
VMSTATE_STRUCT(fifo1, PL041State, 0,
|
|
vmstate_pl041_channel, pl041_channel),
|
|
VMSTATE_STRUCT(codec, PL041State, 0,
|
|
vmstate_lm4549_state, lm4549_state),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property pl041_device_properties[] = {
|
|
DEFINE_AUDIO_PROPERTIES(PL041State, codec.card),
|
|
/* Non-compact FIFO depth property */
|
|
DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
|
|
DEFAULT_FIFO_DEPTH),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pl041_device_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pl041_realize;
|
|
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
|
|
dc->reset = pl041_device_reset;
|
|
dc->vmsd = &vmstate_pl041;
|
|
device_class_set_props(dc, pl041_device_properties);
|
|
}
|
|
|
|
static const TypeInfo pl041_device_info = {
|
|
.name = TYPE_PL041,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PL041State),
|
|
.instance_init = pl041_init,
|
|
.class_init = pl041_device_class_init,
|
|
};
|
|
|
|
static void pl041_register_types(void)
|
|
{
|
|
type_register_static(&pl041_device_info);
|
|
}
|
|
|
|
type_init(pl041_register_types)
|