db1015e92e
Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName"
declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
$(git grep -l '' -- '*.[ch]')
which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
377 lines
13 KiB
C
377 lines
13 KiB
C
/*
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* Xilinx Zynq Baseboard System emulation.
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*
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* Copyright (c) 2010 Xilinx.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
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* Copyright (c) 2012 Petalogix Pty Ltd.
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* Written by Haibing Ma
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/arm/boot.h"
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#include "net/net.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/block/flash.h"
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#include "hw/loader.h"
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#include "hw/misc/zynq-xadc.h"
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#include "hw/ssi/ssi.h"
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#include "hw/usb/chipidea.h"
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#include "qemu/error-report.h"
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#include "hw/sd/sdhci.h"
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#include "hw/char/cadence_uart.h"
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#include "hw/net/cadence_gem.h"
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#include "hw/cpu/a9mpcore.h"
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#include "hw/qdev-clock.h"
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#include "sysemu/reset.h"
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#include "qom/object.h"
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#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
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typedef struct ZynqMachineState ZynqMachineState;
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#define ZYNQ_MACHINE(obj) \
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OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)
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/* board base frequency: 33.333333 MHz */
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#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
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#define NUM_SPI_FLASHES 4
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#define NUM_QSPI_FLASHES 2
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#define NUM_QSPI_BUSSES 2
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#define FLASH_SIZE (64 * 1024 * 1024)
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#define FLASH_SECTOR_SIZE (128 * 1024)
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#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
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#define MPCORE_PERIPHBASE 0xF8F00000
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#define ZYNQ_BOARD_MIDR 0x413FC090
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static const int dma_irqs[8] = {
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46, 47, 48, 49, 72, 73, 74, 75
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};
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#define BOARD_SETUP_ADDR 0x100
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#define SLCR_LOCK_OFFSET 0x004
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#define SLCR_UNLOCK_OFFSET 0x008
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#define SLCR_ARM_PLL_OFFSET 0x100
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#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
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#define SLCR_XILINX_LOCK_KEY 0x767b
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#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
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#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
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extract32((x), 12, 4) << 16)
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/* Write immediate val to address r0 + addr. r0 should contain base offset
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* of the SLCR block. Clobbers r1.
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*/
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#define SLCR_WRITE(addr, val) \
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0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
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0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
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0xe5801000 + (addr)
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struct ZynqMachineState {
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MachineState parent;
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Clock *ps_clk;
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};
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static void zynq_write_board_setup(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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int n;
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uint32_t board_setup_blob[] = {
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0xe3a004f8, /* mov r0, #0xf8000000 */
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SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
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SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
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SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
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0xe12fff1e, /* bx lr */
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};
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for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
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board_setup_blob[n] = tswap32(board_setup_blob[n]);
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}
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rom_add_blob_fixed("board-setup", board_setup_blob,
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sizeof(board_setup_blob), BOARD_SETUP_ADDR);
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}
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static struct arm_boot_info zynq_binfo = {};
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static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_new(TYPE_CADENCE_GEM);
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if (nd->used) {
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qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
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qdev_set_nic_properties(dev, nd);
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}
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, base);
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sysbus_connect_irq(s, 0, irq);
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}
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static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
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bool is_qspi)
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{
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DeviceState *dev;
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SysBusDevice *busdev;
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SSIBus *spi;
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DeviceState *flash_dev;
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int i, j;
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int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
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int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
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dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
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qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
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qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
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qdev_prop_set_uint8(dev, "num-busses", num_busses);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(busdev, &error_fatal);
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sysbus_mmio_map(busdev, 0, base_addr);
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if (is_qspi) {
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sysbus_mmio_map(busdev, 1, 0xFC000000);
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}
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sysbus_connect_irq(busdev, 0, irq);
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for (i = 0; i < num_busses; ++i) {
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char bus_name[16];
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qemu_irq cs_line;
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snprintf(bus_name, 16, "spi%d", i);
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spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
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for (j = 0; j < num_ss; ++j) {
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DriveInfo *dinfo = drive_get_next(IF_MTD);
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flash_dev = qdev_new("n25q128");
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if (dinfo) {
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qdev_prop_set_drive_err(flash_dev, "drive",
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blk_by_legacy_dinfo(dinfo),
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&error_fatal);
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}
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qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
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cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
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sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
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}
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}
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}
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static void zynq_init(MachineState *machine)
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{
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ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
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ARMCPU *cpu;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
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DeviceState *dev, *slcr;
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SysBusDevice *busdev;
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qemu_irq pic[64];
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int n;
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/* max 2GB ram */
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if (machine->ram_size > 2 * GiB) {
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error_report("RAM size more than 2 GiB is not supported");
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exit(EXIT_FAILURE);
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}
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cpu = ARM_CPU(object_new(machine->cpu_type));
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/* By default A9 CPUs have EL3 enabled. This board does not
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* currently support EL3 so the CPU EL3 property is disabled before
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* realization.
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*/
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if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
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object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal);
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}
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object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR,
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&error_fatal);
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object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE,
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&error_fatal);
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qdev_realize(DEVICE(cpu), NULL, &error_fatal);
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/* DDR remapped to address zero. */
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memory_region_add_subregion(address_space_mem, 0, machine->ram);
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/* 256K of on-chip memory */
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memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
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&error_fatal);
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memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
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DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
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/* AMD */
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pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
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dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
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FLASH_SECTOR_SIZE, 1,
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1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
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0);
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/* Create the main clock source, and feed slcr with it */
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zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
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object_property_add_child(OBJECT(zynq_machine), "ps_clk",
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OBJECT(zynq_machine->ps_clk));
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object_unref(OBJECT(zynq_machine->ps_clk));
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clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
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/* Create slcr, keep a pointer to connect clocks */
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slcr = qdev_new("xilinx,zynq_slcr");
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qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
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dev = qdev_new(TYPE_A9MPCORE_PRIV);
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qdev_prop_set_uint32(dev, "num-cpu", 1);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(busdev, &error_fatal);
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sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
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for (n = 0; n < 64; n++) {
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
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zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
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zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
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sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
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sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
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dev = qdev_new(TYPE_CADENCE_UART);
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busdev = SYS_BUS_DEVICE(dev);
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qdev_prop_set_chr(dev, "chardev", serial_hd(0));
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qdev_connect_clock_in(dev, "refclk",
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qdev_get_clock_out(slcr, "uart0_ref_clk"));
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sysbus_realize_and_unref(busdev, &error_fatal);
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sysbus_mmio_map(busdev, 0, 0xE0000000);
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sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
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dev = qdev_new(TYPE_CADENCE_UART);
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busdev = SYS_BUS_DEVICE(dev);
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qdev_prop_set_chr(dev, "chardev", serial_hd(1));
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qdev_connect_clock_in(dev, "refclk",
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qdev_get_clock_out(slcr, "uart1_ref_clk"));
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sysbus_realize_and_unref(busdev, &error_fatal);
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sysbus_mmio_map(busdev, 0, 0xE0001000);
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sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
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sysbus_create_varargs("cadence_ttc", 0xF8001000,
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pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
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sysbus_create_varargs("cadence_ttc", 0xF8002000,
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pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
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gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
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gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
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for (n = 0; n < 2; n++) {
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int hci_irq = n ? 79 : 56;
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hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
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DriveInfo *di;
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BlockBackend *blk;
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DeviceState *carddev;
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/* Compatible with:
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* - SD Host Controller Specification Version 2.0 Part A2
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* - SDIO Specification Version 2.0
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* - MMC Specification Version 3.31
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*/
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dev = qdev_new(TYPE_SYSBUS_SDHCI);
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qdev_prop_set_uint8(dev, "sd-spec-version", 2);
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qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
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di = drive_get_next(IF_SD);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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carddev = qdev_new(TYPE_SD_CARD);
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qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
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qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
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&error_fatal);
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}
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dev = qdev_new(TYPE_ZYNQ_XADC);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
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dev = qdev_new("pl330");
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qdev_prop_set_uint8(dev, "num_chnls", 8);
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qdev_prop_set_uint8(dev, "num_periph_req", 4);
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qdev_prop_set_uint8(dev, "num_events", 16);
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qdev_prop_set_uint8(dev, "data_width", 64);
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qdev_prop_set_uint8(dev, "wr_cap", 8);
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qdev_prop_set_uint8(dev, "wr_q_dep", 16);
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qdev_prop_set_uint8(dev, "rd_cap", 8);
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qdev_prop_set_uint8(dev, "rd_q_dep", 16);
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qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(busdev, &error_fatal);
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sysbus_mmio_map(busdev, 0, 0xF8003000);
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sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
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for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
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sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
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}
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dev = qdev_new("xlnx.ps7-dev-cfg");
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(busdev, &error_fatal);
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sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
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sysbus_mmio_map(busdev, 0, 0xF8007000);
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zynq_binfo.ram_size = machine->ram_size;
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zynq_binfo.nb_cpus = 1;
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zynq_binfo.board_id = 0xd32;
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zynq_binfo.loader_start = 0;
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zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
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zynq_binfo.write_board_setup = zynq_write_board_setup;
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arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
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}
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static void zynq_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
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mc->init = zynq_init;
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mc->max_cpus = 1;
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mc->no_sdcard = 1;
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mc->ignore_memory_transaction_failures = true;
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
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mc->default_ram_id = "zynq.ext_ram";
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}
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static const TypeInfo zynq_machine_type = {
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.name = TYPE_ZYNQ_MACHINE,
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.parent = TYPE_MACHINE,
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.class_init = zynq_machine_class_init,
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.instance_size = sizeof(ZynqMachineState),
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};
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static void zynq_machine_register_types(void)
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{
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type_register_static(&zynq_machine_type);
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}
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type_init(zynq_machine_register_types)
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