Alistair Francis daf866b606 target/riscv: Consolidate RV32/64 32-bit instructions ... This patch removes the insn32-64.decode decode file and consolidates the instructions into the general RISC-V insn32.decode decode tree. This means that all of the instructions are avaliable in both the 32-bit and 64-bit builds. This also means that we run a check to ensure we are running a 64-bit softmmu before we execute the 64-bit only instructions. This allows us to include the 32-bit instructions in the 64-bit build, while also ensuring that 32-bit only software can not execute the instructions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com		2021-05-11 20:02:07 +10:00
..
insn_trans	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
cpu_bits.h	target/riscv: Remove the unused HSTATUS_WPRI macro	2021-05-11 20:02:07 +10:00
cpu_helper.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Remove the hardcoded RVXLEN macro	2021-05-11 20:02:07 +10:00
cpu.h	target/riscv: Remove the hardcoded RVXLEN macro	2021-05-11 20:02:07 +10:00
csr.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: Use RISCVException enum for CSR access	2021-05-11 20:02:06 +10:00
helper.h	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32.decode	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Remove privilege v1.9 specific CSR related code	2021-05-11 20:01:10 +10:00
meson.build	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
monitor.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
op_helper.c	target/riscv: Use RISCVException enum for CSR access	2021-05-11 20:02:06 +10:00
pmp.c	target/riscv/pmp: Remove outdated comment	2021-05-11 20:02:06 +10:00
pmp.h	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00