Peter Maydell 13557fd392 hw/timer/imx_epit: Avoid assertion when CR.SWR is written ... The imx_epit device has a software-controllable reset triggered by setting the SWR bit in the CR register. An error in commit cc2722ec83 means that we will end up assert()ing if the guest does this, because the code in imx_epit_write() starts ptimer transactions, and then imx_epit_reset() also starts ptimer transactions, triggering "ptimer_transaction_begin: Assertion `!s->in_transaction' failed". The cleanest way to avoid this double-transaction is to move the start-transaction for the CR write handling down below the check of the SWR bit. Fixes: https://bugs.launchpad.net/qemu/+bug/1880424 Fixes: cc2722ec83 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200727154550.3409-1-peter.maydell@linaro.org		2020-08-03 17:56:11 +01:00
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a9gtimer.c
allwinner-a10-pit.c
altera_timer.c
arm_mptimer.c
arm_timer.c
armv7m_systick.c
aspeed_timer.c
avr_timer16.c
bcm2835_systmr.c
cadence_ttc.c
cmsdk-apb-dualtimer.c
cmsdk-apb-timer.c
digic-timer.c
etraxfs_timer.c
exynos4210_mct.c
exynos4210_pwm.c
grlib_gptimer.c
hpet.c
i8254_common.c
i8254.c
imx_epit.c	hw/timer/imx_epit: Avoid assertion when CR.SWR is written	2020-08-03 17:56:11 +01:00
imx_gpt.c
Kconfig
lm32_timer.c
Makefile.objs
milkymist-sysctl.c
mips_gictimer.c
mss-timer.c
nrf51_timer.c
omap_gptimer.c
omap_synctimer.c
puv3_ost.c
pxa2xx_timer.c
renesas_cmt.c
renesas_tmr.c
sh_timer.c
slavio_timer.c
stm32f2xx_timer.c
trace-events
xilinx_timer.c