qemu/target
Richard Henderson d902ae7558 target/arm: Fold secure and non-secure a-profile mmu indexes
For a-profile aarch64, which does not bank system registers, it takes
quite a lot of code to switch between security states.  In the process,
registers such as TCR_EL{1,2} must be swapped, which in itself requires
the flushing of softmmu tlbs.  Therefore it doesn't buy us anything to
separate tlbs by security state.

Retain the distinction between Stage2 and Stage2_S.

This will be important as we implement FEAT_RME, and do not wish to
add a third set of mmu indexes for Realm state.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-10 14:52:24 +01:00
..
alpha hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
arm target/arm: Fold secure and non-secure a-profile mmu indexes 2022-10-10 14:52:24 +01:00
avr accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
cris hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
hexagon Make store handling faster and more robust 2022-10-05 10:17:32 -04:00
hppa accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
i386 monitor: expose monitor_puts to rest of code 2022-10-06 11:53:40 +01:00
loongarch accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
m68k hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
microblaze accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
mips accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
nios2 hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
openrisc accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
ppc hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
riscv accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
rx accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
s390x hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
sh4 target/sh4: Fix TB_FLAG_UNALIGN 2022-10-04 12:33:05 -07:00
sparc accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
tricore accel/tcg: Introduce tb_pc and log_pc 2022-10-04 12:13:12 -07:00
xtensa hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00