61b2440503
The SDRAM controller is shared across almost all 405 and 440 embedded processors, with some slight differences such as the sizes supported for each memory bank. Code movement only; no functional changes. Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6061 c046a42c-6fe2-441c-8c8c-71466251a162
106 lines
4.1 KiB
C
106 lines
4.1 KiB
C
/*
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* QEMU PowerPC 405 shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if !defined(PPC_405_H)
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#define PPC_405_H
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#include "ppc4xx.h"
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/* Bootinfo as set-up by u-boot */
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typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
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struct ppc4xx_bd_info_t {
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uint32_t bi_memstart;
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uint32_t bi_memsize;
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uint32_t bi_flashstart;
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uint32_t bi_flashsize;
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uint32_t bi_flashoffset; /* 0x10 */
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uint32_t bi_sramstart;
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uint32_t bi_sramsize;
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uint32_t bi_bootflags;
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uint32_t bi_ipaddr; /* 0x20 */
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uint8_t bi_enetaddr[6];
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uint16_t bi_ethspeed;
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uint32_t bi_intfreq;
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uint32_t bi_busfreq; /* 0x30 */
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uint32_t bi_baudrate;
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uint8_t bi_s_version[4];
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uint8_t bi_r_version[32];
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uint32_t bi_procfreq;
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uint32_t bi_plb_busfreq;
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uint32_t bi_pci_busfreq;
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uint8_t bi_pci_enetaddr[6];
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uint32_t bi_pci_enetaddr2[6];
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uint32_t bi_opbfreq;
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uint32_t bi_iic_fast[2];
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};
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/* PowerPC 405 core */
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
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uint32_t flags);
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/* PowerPC 4xx peripheral local bus arbitrer */
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void ppc4xx_plb_init (CPUState *env);
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/* PLB to OPB bridge */
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void ppc4xx_pob_init (CPUState *env);
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/* OPB arbitrer */
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void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset);
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/* Peripheral controller */
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void ppc405_ebc_init (CPUState *env);
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/* DMA controller */
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void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
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/* GPIO */
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void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset);
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/* Serial ports */
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void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, qemu_irq irq,
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CharDriverState *chr);
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/* On Chip Memory */
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void ppc405_ocm_init (CPUState *env, unsigned long offset);
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/* I2C controller */
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void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, qemu_irq irq);
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/* General purpose timers */
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void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
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target_phys_addr_t offset, qemu_irq irq[5]);
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/* Memory access layer */
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void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
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/* PowerPC 405 microcontrollers */
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CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
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target_phys_addr_t ram_sizes[4],
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uint32_t sysclk, qemu_irq **picp,
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ram_addr_t *offsetp, int do_init);
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CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
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target_phys_addr_t ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp,
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ram_addr_t *offsetp, int do_init);
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/* IBM STBxxx microcontrollers */
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CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
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target_phys_addr_t ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp,
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ram_addr_t *offsetp);
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#endif /* !defined(PPC_405_H) */
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