b01422622b
Currently the ptimer design uses a QEMU bottom-half as its mechanism for calling back into the device model using the ptimer when the timer has expired. Unfortunately this design is fatally flawed, because it means that there is a lag between the ptimer updating its own state and the device callback function updating device state, and guest accesses to device registers between the two can return inconsistent device state. We want to replace the bottom-half design with one where the guest device's callback is called either immediately (when the ptimer triggers by timeout) or when the device model code closes a transaction-begin/end section (when the ptimer triggers because the device model changed the ptimer's count value or other state). As the first step, rename ptimer_init() to ptimer_init_with_bh(), to free up the ptimer_init() name for the new API. We can then convert all the ptimer users away from ptimer_init_with_bh() before removing it entirely. (Commit created with git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/' and three overlong lines folded by hand.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191008171740.9679-2-peter.maydell@linaro.org
324 lines
9.8 KiB
C
324 lines
9.8 KiB
C
/*
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* Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Copyright (c) 2011 Linaro Limited
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* Written by Paul Brook, Peter Maydell
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "hw/qdev-properties.h"
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#include "hw/timer/arm_mptimer.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "hw/core/cpu.h"
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#define PTIMER_POLICY \
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(PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \
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PTIMER_POLICY_CONTINUOUS_TRIGGER | \
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PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | \
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PTIMER_POLICY_NO_IMMEDIATE_RELOAD | \
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PTIMER_POLICY_NO_COUNTER_ROUND_DOWN)
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/* This device implements the per-cpu private timer and watchdog block
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* which is used in both the ARM11MPCore and Cortex-A9MP.
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*/
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static inline int get_current_cpu(ARMMPTimerState *s)
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{
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int cpu_id = current_cpu ? current_cpu->cpu_index : 0;
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if (cpu_id >= s->num_cpu) {
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hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
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s->num_cpu, cpu_id);
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}
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return cpu_id;
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}
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static inline void timerblock_update_irq(TimerBlock *tb)
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{
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qemu_set_irq(tb->irq, tb->status && (tb->control & 4));
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}
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/* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
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static inline uint32_t timerblock_scale(uint32_t control)
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{
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return (((control >> 8) & 0xff) + 1) * 10;
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}
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static inline void timerblock_set_count(struct ptimer_state *timer,
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uint32_t control, uint64_t *count)
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{
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/* PTimer would trigger interrupt for periodic timer when counter set
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* to 0, MPtimer under certain condition only.
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*/
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if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) {
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*count = ptimer_get_limit(timer);
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}
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ptimer_set_count(timer, *count);
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}
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static inline void timerblock_run(struct ptimer_state *timer,
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uint32_t control, uint32_t load)
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{
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if ((control & 1) && ((control & 0xff00) || load != 0)) {
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ptimer_run(timer, !(control & 2));
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}
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}
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static void timerblock_tick(void *opaque)
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{
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TimerBlock *tb = (TimerBlock *)opaque;
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/* Periodic timer with load = 0 and prescaler != 0 would re-trigger
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* IRQ after one period, otherwise it either stops or wraps around.
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*/
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if ((tb->control & 2) && (tb->control & 0xff00) == 0 &&
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ptimer_get_limit(tb->timer) == 0) {
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ptimer_stop(tb->timer);
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}
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tb->status = 1;
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timerblock_update_irq(tb);
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}
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static uint64_t timerblock_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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TimerBlock *tb = (TimerBlock *)opaque;
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switch (addr) {
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case 0: /* Load */
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return ptimer_get_limit(tb->timer);
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case 4: /* Counter. */
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return ptimer_get_count(tb->timer);
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case 8: /* Control. */
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return tb->control;
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case 12: /* Interrupt status. */
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return tb->status;
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default:
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return 0;
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}
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}
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static void timerblock_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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TimerBlock *tb = (TimerBlock *)opaque;
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uint32_t control = tb->control;
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switch (addr) {
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case 0: /* Load */
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/* Setting load to 0 stops the timer without doing the tick if
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* prescaler = 0.
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*/
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if ((control & 1) && (control & 0xff00) == 0 && value == 0) {
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ptimer_stop(tb->timer);
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}
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ptimer_set_limit(tb->timer, value, 1);
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timerblock_run(tb->timer, control, value);
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break;
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case 4: /* Counter. */
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/* Setting counter to 0 stops the one-shot timer, or periodic with
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* load = 0, without doing the tick if prescaler = 0.
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*/
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if ((control & 1) && (control & 0xff00) == 0 && value == 0 &&
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(!(control & 2) || ptimer_get_limit(tb->timer) == 0)) {
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ptimer_stop(tb->timer);
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}
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timerblock_set_count(tb->timer, control, &value);
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timerblock_run(tb->timer, control, value);
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break;
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case 8: /* Control. */
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if ((control & 3) != (value & 3)) {
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ptimer_stop(tb->timer);
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}
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if ((control & 0xff00) != (value & 0xff00)) {
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ptimer_set_period(tb->timer, timerblock_scale(value));
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}
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if (value & 1) {
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uint64_t count = ptimer_get_count(tb->timer);
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/* Re-load periodic timer counter if needed. */
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if ((value & 2) && count == 0) {
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timerblock_set_count(tb->timer, value, &count);
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}
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timerblock_run(tb->timer, value, count);
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}
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tb->control = value;
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break;
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case 12: /* Interrupt status. */
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tb->status &= ~value;
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timerblock_update_irq(tb);
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break;
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}
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}
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/* Wrapper functions to implement the "read timer/watchdog for
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* the current CPU" memory regions.
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*/
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static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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ARMMPTimerState *s = (ARMMPTimerState *)opaque;
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int id = get_current_cpu(s);
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return timerblock_read(&s->timerblock[id], addr, size);
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}
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static void arm_thistimer_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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ARMMPTimerState *s = (ARMMPTimerState *)opaque;
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int id = get_current_cpu(s);
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timerblock_write(&s->timerblock[id], addr, value, size);
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}
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static const MemoryRegionOps arm_thistimer_ops = {
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.read = arm_thistimer_read,
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.write = arm_thistimer_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const MemoryRegionOps timerblock_ops = {
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.read = timerblock_read,
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.write = timerblock_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void timerblock_reset(TimerBlock *tb)
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{
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tb->control = 0;
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tb->status = 0;
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if (tb->timer) {
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ptimer_stop(tb->timer);
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ptimer_set_limit(tb->timer, 0, 1);
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ptimer_set_period(tb->timer, timerblock_scale(0));
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}
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}
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static void arm_mptimer_reset(DeviceState *dev)
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{
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ARMMPTimerState *s = ARM_MPTIMER(dev);
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int i;
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for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
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timerblock_reset(&s->timerblock[i]);
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}
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}
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static void arm_mptimer_init_with_bh(Object *obj)
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{
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ARMMPTimerState *s = ARM_MPTIMER(obj);
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memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s,
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"arm_mptimer_timer", 0x20);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static void arm_mptimer_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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ARMMPTimerState *s = ARM_MPTIMER(dev);
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int i;
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if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) {
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error_setg(errp, "num-cpu must be between 1 and %d",
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ARM_MPTIMER_MAX_CPUS);
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return;
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}
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/* We implement one timer block per CPU, and expose multiple MMIO regions:
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* * region 0 is "timer for this core"
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* * region 1 is "timer for core 0"
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* * region 2 is "timer for core 1"
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* and so on.
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* The outgoing interrupt lines are
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* * timer for core 0
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* * timer for core 1
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* and so on.
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*/
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for (i = 0; i < s->num_cpu; i++) {
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TimerBlock *tb = &s->timerblock[i];
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QEMUBH *bh = qemu_bh_new(timerblock_tick, tb);
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tb->timer = ptimer_init_with_bh(bh, PTIMER_POLICY);
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sysbus_init_irq(sbd, &tb->irq);
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memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
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"arm_mptimer_timerblock", 0x20);
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sysbus_init_mmio(sbd, &tb->iomem);
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}
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}
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static const VMStateDescription vmstate_timerblock = {
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.name = "arm_mptimer_timerblock",
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, TimerBlock),
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VMSTATE_UINT32(status, TimerBlock),
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VMSTATE_PTIMER(timer, TimerBlock),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_arm_mptimer = {
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.name = "arm_mptimer",
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
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3, vmstate_timerblock, TimerBlock),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property arm_mptimer_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void arm_mptimer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = arm_mptimer_realize;
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dc->vmsd = &vmstate_arm_mptimer;
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dc->reset = arm_mptimer_reset;
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dc->props = arm_mptimer_properties;
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}
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static const TypeInfo arm_mptimer_info = {
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.name = TYPE_ARM_MPTIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMMPTimerState),
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.instance_init = arm_mptimer_init_with_bh,
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.class_init = arm_mptimer_class_init,
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};
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static void arm_mptimer_register_types(void)
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{
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type_register_static(&arm_mptimer_info);
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}
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type_init(arm_mptimer_register_types)
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