d783d1fe58
This will simplify the definition of new SoCs, like the AST2600 which should use a slightly different address space and have a different set of controllers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
409 lines
14 KiB
C
409 lines
14 KiB
C
/*
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* OpenPOWER Palmetto BMC
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/aspeed.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/boards.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "hw/misc/pca9552.h"
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#include "hw/misc/tmp105.h"
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#include "qemu/log.h"
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#include "sysemu/block-backend.h"
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#include "hw/loader.h"
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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static struct arm_boot_info aspeed_board_binfo = {
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.board_id = -1, /* device-tree-only board */
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.nb_cpus = 1,
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};
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struct AspeedBoardState {
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AspeedSoCState soc;
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MemoryRegion ram;
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MemoryRegion max_ram;
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};
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/* Palmetto hardware value: 0x120CE416 */
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#define PALMETTO_BMC_HW_STRAP1 ( \
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SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
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SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
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SCU_AST2400_HW_STRAP_ACPI_DIS | \
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SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
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SCU_HW_STRAP_VGA_CLASS_CODE | \
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SCU_HW_STRAP_LPC_RESET_PIN | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
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SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
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SCU_HW_STRAP_SPI_WIDTH | \
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
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/* AST2500 evb hardware value: 0xF100C2E6 */
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#define AST2500_EVB_HW_STRAP1 (( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_HW_STRAP_MAC1_RGMII | \
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SCU_HW_STRAP_MAC0_RGMII) & \
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~SCU_HW_STRAP_2ND_BOOT_WDT)
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/* Romulus hardware value: 0xF10AD206 */
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#define ROMULUS_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
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/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
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#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
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/*
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* The max ram region is for firmwares that scan the address space
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* with load/store to guess how much RAM the SoC has.
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*/
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static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
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{
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return 0;
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}
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static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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/* Discard writes */
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}
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static const MemoryRegionOps max_ram_ops = {
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.read = max_ram_read,
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.write = max_ram_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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#define FIRMWARE_ADDR 0x0
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static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
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Error **errp)
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{
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BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
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uint8_t *storage;
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int64_t size;
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/* The block backend size should have already been 'validated' by
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* the creation of the m25p80 object.
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*/
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size = blk_getlength(blk);
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if (size <= 0) {
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error_setg(errp, "failed to get flash size");
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return;
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}
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if (rom_size > size) {
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rom_size = size;
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}
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storage = g_new0(uint8_t, rom_size);
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if (blk_pread(blk, 0, storage, rom_size) < 0) {
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error_setg(errp, "failed to read the initial flash content");
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return;
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}
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rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
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g_free(storage);
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}
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static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
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Error **errp)
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{
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int i ;
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for (i = 0; i < s->num_cs; ++i) {
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AspeedSMCFlash *fl = &s->flashes[i];
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DriveInfo *dinfo = drive_get_next(IF_MTD);
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qemu_irq cs_line;
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fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
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if (dinfo) {
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qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
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errp);
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}
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qdev_init_nofail(fl->flash);
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cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
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sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
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}
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}
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static void aspeed_board_init(MachineState *machine,
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const AspeedBoardConfig *cfg)
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{
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AspeedBoardState *bmc;
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AspeedSoCClass *sc;
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DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
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ram_addr_t max_ram_size;
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bmc = g_new0(AspeedBoardState, 1);
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object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
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(sizeof(bmc->soc)), cfg->soc_name, &error_abort,
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NULL);
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sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
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object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
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&error_abort);
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object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
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&error_abort);
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object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
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&error_abort);
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if (machine->kernel_filename) {
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/*
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* When booting with a -kernel command line there is no u-boot
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* that runs to unlock the SCU. In this case set the default to
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* be unlocked as the kernel expects
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*/
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object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY,
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"hw-prot-key", &error_abort);
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}
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object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
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&error_abort);
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/*
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* Allocate RAM after the memory controller has checked the size
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* was valid. If not, a default value is used.
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*/
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ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size",
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&error_abort);
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memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
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memory_region_add_subregion(get_system_memory(),
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sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
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object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
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&error_abort);
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max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
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&error_abort);
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memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
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"max_ram", max_ram_size - ram_size);
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memory_region_add_subregion(get_system_memory(),
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sc->info->memmap[ASPEED_SDRAM] + ram_size,
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&bmc->max_ram);
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aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
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aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
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/* Install first FMC flash content as a boot rom. */
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if (drive0) {
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AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
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MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
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/*
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* create a ROM region using the default mapping window size of
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* the flash module. The window size is 64MB for the AST2400
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* SoC and 128MB for the AST2500 SoC, which is twice as big as
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* needed by the flash modules of the Aspeed machines.
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*/
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memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
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fl->size, &error_abort);
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memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
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boot_rom);
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write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
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}
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aspeed_board_binfo.kernel_filename = machine->kernel_filename;
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aspeed_board_binfo.initrd_filename = machine->initrd_filename;
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aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
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aspeed_board_binfo.ram_size = ram_size;
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aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
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if (cfg->i2c_init) {
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cfg->i2c_init(bmc);
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}
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arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
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}
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static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
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{
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AspeedSoCState *soc = &bmc->soc;
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DeviceState *dev;
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uint8_t *eeprom_buf = g_malloc0(32 * 1024);
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/* The palmetto platform expects a ds3231 RTC but a ds1338 is
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* enough to provide basic RTC features. Alarms will be missing */
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
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smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
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eeprom_buf);
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/* add a TMP423 temperature sensor */
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dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
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"tmp423", 0x4c);
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object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
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object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
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object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
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object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
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}
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static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
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{
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AspeedSoCState *soc = &bmc->soc;
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uint8_t *eeprom_buf = g_malloc0(8 * 1024);
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smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
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eeprom_buf);
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/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7),
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TYPE_TMP105, 0x4d);
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/* The AST2500 EVB does not have an RTC. Let's pretend that one is
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* plugged on the I2C bus header */
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
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}
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static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
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{
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AspeedSoCState *soc = &bmc->soc;
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/* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
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* good enough */
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
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}
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static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
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{
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AspeedSoCState *soc = &bmc->soc;
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uint8_t *eeprom_buf = g_malloc0(8 * 1024);
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552,
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0x60);
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
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/* The Witherspoon expects a TMP275 but a TMP105 is compatible */
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105,
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0x4a);
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/* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
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* good enough */
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
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smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
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eeprom_buf);
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i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552,
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0x60);
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}
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static void aspeed_machine_init(MachineState *machine)
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{
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AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
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aspeed_board_init(machine, amc->board);
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}
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static void aspeed_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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const AspeedBoardConfig *board = data;
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mc->desc = board->desc;
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mc->init = aspeed_machine_init;
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mc->max_cpus = 1;
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mc->no_sdcard = 1;
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mc->no_floppy = 1;
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mc->no_cdrom = 1;
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mc->no_parallel = 1;
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if (board->ram) {
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mc->default_ram_size = board->ram;
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}
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amc->board = board;
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}
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static const TypeInfo aspeed_machine_type = {
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.name = TYPE_ASPEED_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(AspeedMachine),
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.class_size = sizeof(AspeedMachineClass),
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.abstract = true,
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};
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static const AspeedBoardConfig aspeed_boards[] = {
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{
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.name = MACHINE_TYPE_NAME("palmetto-bmc"),
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.desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)",
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.soc_name = "ast2400-a1",
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.hw_strap1 = PALMETTO_BMC_HW_STRAP1,
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.fmc_model = "n25q256a",
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.spi_model = "mx25l25635e",
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.num_cs = 1,
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.i2c_init = palmetto_bmc_i2c_init,
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.ram = 256 * MiB,
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}, {
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.name = MACHINE_TYPE_NAME("ast2500-evb"),
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.desc = "Aspeed AST2500 EVB (ARM1176)",
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.soc_name = "ast2500-a1",
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.hw_strap1 = AST2500_EVB_HW_STRAP1,
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.fmc_model = "w25q256",
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.spi_model = "mx25l25635e",
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.num_cs = 1,
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.i2c_init = ast2500_evb_i2c_init,
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.ram = 512 * MiB,
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}, {
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.name = MACHINE_TYPE_NAME("romulus-bmc"),
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.desc = "OpenPOWER Romulus BMC (ARM1176)",
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.soc_name = "ast2500-a1",
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.hw_strap1 = ROMULUS_BMC_HW_STRAP1,
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.fmc_model = "n25q256a",
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.spi_model = "mx66l1g45g",
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.num_cs = 2,
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.i2c_init = romulus_bmc_i2c_init,
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.ram = 512 * MiB,
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}, {
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.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
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.desc = "OpenPOWER Witherspoon BMC (ARM1176)",
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.soc_name = "ast2500-a1",
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.hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
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.fmc_model = "mx25l25635e",
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.spi_model = "mx66l1g45g",
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.num_cs = 2,
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.i2c_init = witherspoon_bmc_i2c_init,
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.ram = 512 * MiB,
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},
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};
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static void aspeed_machine_types(void)
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{
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int i;
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type_register_static(&aspeed_machine_type);
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for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) {
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TypeInfo ti = {
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.name = aspeed_boards[i].name,
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.parent = TYPE_ASPEED_MACHINE,
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.class_init = aspeed_machine_class_init,
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.class_data = (void *)&aspeed_boards[i],
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};
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type_register(&ti);
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}
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}
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type_init(aspeed_machine_types)
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