461 lines
12 KiB
C
461 lines
12 KiB
C
/*
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* Alpha emulation cpu definitions for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if !defined (__CPU_ALPHA_H__)
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#define __CPU_ALPHA_H__
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#include "config.h"
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#define TARGET_LONG_BITS 64
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#define CPUState struct CPUAlphaState
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#include "cpu-defs.h"
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#include <setjmp.h>
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#include "softfloat.h"
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#define TARGET_HAS_ICE 1
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#define ELF_MACHINE EM_ALPHA
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#define ICACHE_LINE_SIZE 32
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#define DCACHE_LINE_SIZE 32
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#define TARGET_PAGE_BITS 13
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#define VA_BITS 43
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/* Alpha major type */
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enum {
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ALPHA_EV3 = 1,
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ALPHA_EV4 = 2,
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ALPHA_SIM = 3,
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ALPHA_LCA = 4,
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ALPHA_EV5 = 5, /* 21164 */
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ALPHA_EV45 = 6, /* 21064A */
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ALPHA_EV56 = 7, /* 21164A */
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};
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/* EV4 minor type */
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enum {
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ALPHA_EV4_2 = 0,
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ALPHA_EV4_3 = 1,
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};
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/* LCA minor type */
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enum {
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ALPHA_LCA_1 = 1, /* 21066 */
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ALPHA_LCA_2 = 2, /* 20166 */
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ALPHA_LCA_3 = 3, /* 21068 */
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ALPHA_LCA_4 = 4, /* 21068 */
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ALPHA_LCA_5 = 5, /* 21066A */
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ALPHA_LCA_6 = 6, /* 21068A */
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};
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/* EV5 minor type */
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enum {
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ALPHA_EV5_1 = 1, /* Rev BA, CA */
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ALPHA_EV5_2 = 2, /* Rev DA, EA */
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ALPHA_EV5_3 = 3, /* Pass 3 */
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ALPHA_EV5_4 = 4, /* Pass 3.2 */
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ALPHA_EV5_5 = 5, /* Pass 4 */
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};
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/* EV45 minor type */
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enum {
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ALPHA_EV45_1 = 1, /* Pass 1 */
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ALPHA_EV45_2 = 2, /* Pass 1.1 */
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ALPHA_EV45_3 = 3, /* Pass 2 */
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};
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/* EV56 minor type */
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enum {
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ALPHA_EV56_1 = 1, /* Pass 1 */
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ALPHA_EV56_2 = 2, /* Pass 2 */
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};
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enum {
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IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
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IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
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IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
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IMPLVER_21364 = 3, /* EV7 & EV79 */
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};
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enum {
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AMASK_BWX = 0x00000001,
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AMASK_FIX = 0x00000002,
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AMASK_CIX = 0x00000004,
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AMASK_MVI = 0x00000100,
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AMASK_TRAP = 0x00000200,
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AMASK_PREFETCH = 0x00001000,
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};
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enum {
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VAX_ROUND_NORMAL = 0,
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VAX_ROUND_CHOPPED,
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};
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enum {
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IEEE_ROUND_NORMAL = 0,
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IEEE_ROUND_DYNAMIC,
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IEEE_ROUND_PLUS,
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IEEE_ROUND_MINUS,
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IEEE_ROUND_CHOPPED,
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};
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/* IEEE floating-point operations encoding */
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/* Trap mode */
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enum {
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FP_TRAP_I = 0x0,
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FP_TRAP_U = 0x1,
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FP_TRAP_S = 0x4,
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FP_TRAP_SU = 0x5,
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FP_TRAP_SUI = 0x7,
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};
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/* Rounding mode */
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enum {
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FP_ROUND_CHOPPED = 0x0,
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FP_ROUND_MINUS = 0x1,
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FP_ROUND_NORMAL = 0x2,
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FP_ROUND_DYNAMIC = 0x3,
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};
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/* Internal processor registers */
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/* XXX: TOFIX: most of those registers are implementation dependant */
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enum {
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/* Ebox IPRs */
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IPR_CC = 0xC0, /* 21264 */
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IPR_CC_CTL = 0xC1, /* 21264 */
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#define IPR_CC_CTL_ENA_SHIFT 32
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#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
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IPR_VA = 0xC2, /* 21264 */
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IPR_VA_CTL = 0xC4, /* 21264 */
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#define IPR_VA_CTL_VA_48_SHIFT 1
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#define IPR_VA_CTL_VPTB_SHIFT 30
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IPR_VA_FORM = 0xC3, /* 21264 */
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/* Ibox IPRs */
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IPR_ITB_TAG = 0x00, /* 21264 */
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IPR_ITB_PTE = 0x01, /* 21264 */
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IPR_ITB_IAP = 0x02,
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IPR_ITB_IA = 0x03, /* 21264 */
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IPR_ITB_IS = 0x04, /* 21264 */
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IPR_PMPC = 0x05,
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IPR_EXC_ADDR = 0x06, /* 21264 */
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IPR_IVA_FORM = 0x07, /* 21264 */
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IPR_CM = 0x09, /* 21264 */
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#define IPR_CM_SHIFT 3
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#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */
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IPR_IER = 0x0A, /* 21264 */
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#define IPR_IER_MASK 0x0000007fffffe000ULL
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IPR_IER_CM = 0x0B, /* 21264: = CM | IER */
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IPR_SIRR = 0x0C, /* 21264 */
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#define IPR_SIRR_SHIFT 14
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#define IPR_SIRR_MASK 0x7fff
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IPR_ISUM = 0x0D, /* 21264 */
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IPR_HW_INT_CLR = 0x0E, /* 21264 */
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IPR_EXC_SUM = 0x0F,
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IPR_PAL_BASE = 0x10,
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IPR_I_CTL = 0x11,
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#define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */
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#define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */
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#define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */
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#define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */
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#define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */
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#define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */
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#define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */
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#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
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IPR_I_STAT = 0x16, /* 21264 */
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IPR_IC_FLUSH = 0x13, /* 21264 */
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IPR_IC_FLUSH_ASM = 0x12, /* 21264 */
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IPR_CLR_MAP = 0x15,
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IPR_SLEEP = 0x17,
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IPR_PCTX = 0x40,
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IPR_PCTX_ASN = 0x01, /* field */
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#define IPR_PCTX_ASN_SHIFT 39
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IPR_PCTX_ASTER = 0x02, /* field */
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#define IPR_PCTX_ASTER_SHIFT 5
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IPR_PCTX_ASTRR = 0x04, /* field */
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#define IPR_PCTX_ASTRR_SHIFT 9
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IPR_PCTX_PPCE = 0x08, /* field */
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#define IPR_PCTX_PPCE_SHIFT 1
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IPR_PCTX_FPE = 0x10, /* field */
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#define IPR_PCTX_FPE_SHIFT 2
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IPR_PCTX_ALL = 0x5f, /* all fields */
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IPR_PCTR_CTL = 0x14, /* 21264 */
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/* Mbox IPRs */
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IPR_DTB_TAG0 = 0x20, /* 21264 */
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IPR_DTB_TAG1 = 0xA0, /* 21264 */
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IPR_DTB_PTE0 = 0x21, /* 21264 */
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IPR_DTB_PTE1 = 0xA1, /* 21264 */
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IPR_DTB_ALTMODE = 0xA6,
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IPR_DTB_ALTMODE0 = 0x26, /* 21264 */
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#define IPR_DTB_ALTMODE_MASK 3
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IPR_DTB_IAP = 0xA2,
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IPR_DTB_IA = 0xA3, /* 21264 */
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IPR_DTB_IS0 = 0x24,
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IPR_DTB_IS1 = 0xA4,
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IPR_DTB_ASN0 = 0x25, /* 21264 */
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IPR_DTB_ASN1 = 0xA5, /* 21264 */
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#define IPR_DTB_ASN_SHIFT 56
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IPR_MM_STAT = 0x27, /* 21264 */
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IPR_M_CTL = 0x28, /* 21264 */
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#define IPR_M_CTL_SPE_SHIFT 1
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#define IPR_M_CTL_SPE_MASK 7
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IPR_DC_CTL = 0x29, /* 21264 */
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IPR_DC_STAT = 0x2A, /* 21264 */
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/* Cbox IPRs */
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IPR_C_DATA = 0x2B,
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IPR_C_SHIFT = 0x2C,
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IPR_ASN,
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IPR_ASTEN,
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IPR_ASTSR,
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IPR_DATFX,
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IPR_ESP,
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IPR_FEN,
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IPR_IPIR,
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IPR_IPL,
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IPR_KSP,
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IPR_MCES,
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IPR_PERFMON,
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IPR_PCBB,
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IPR_PRBR,
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IPR_PTBR,
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IPR_SCBB,
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IPR_SISR,
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IPR_SSP,
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IPR_SYSPTBR,
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IPR_TBCHK,
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IPR_TBIA,
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IPR_TBIAP,
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IPR_TBIS,
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IPR_TBISD,
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IPR_TBISI,
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IPR_USP,
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IPR_VIRBND,
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IPR_VPTB,
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IPR_WHAMI,
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IPR_ALT_MODE,
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IPR_LAST,
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};
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typedef struct CPUAlphaState CPUAlphaState;
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typedef struct pal_handler_t pal_handler_t;
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struct pal_handler_t {
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/* Reset */
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void (*reset)(CPUAlphaState *env);
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/* Uncorrectable hardware error */
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void (*machine_check)(CPUAlphaState *env);
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/* Arithmetic exception */
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void (*arithmetic)(CPUAlphaState *env);
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/* Interrupt / correctable hardware error */
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void (*interrupt)(CPUAlphaState *env);
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/* Data fault */
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void (*dfault)(CPUAlphaState *env);
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/* DTB miss pal */
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void (*dtb_miss_pal)(CPUAlphaState *env);
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/* DTB miss native */
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void (*dtb_miss_native)(CPUAlphaState *env);
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/* Unaligned access */
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void (*unalign)(CPUAlphaState *env);
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/* ITB miss */
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void (*itb_miss)(CPUAlphaState *env);
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/* Instruction stream access violation */
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void (*itb_acv)(CPUAlphaState *env);
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/* Reserved or privileged opcode */
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void (*opcdec)(CPUAlphaState *env);
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/* Floating point exception */
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void (*fen)(CPUAlphaState *env);
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/* Call pal instruction */
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void (*call_pal)(CPUAlphaState *env, uint32_t palcode);
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};
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#define NB_MMU_MODES 4
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struct CPUAlphaState {
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uint64_t ir[31];
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float64 fir[31];
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float_status fp_status;
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uint64_t fpcr;
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uint64_t pc;
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uint64_t lock;
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uint32_t pcc[2];
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uint64_t ipr[IPR_LAST];
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uint64_t ps;
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uint64_t unique;
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int saved_mode; /* Used for HW_LD / HW_ST */
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int intr_flag; /* For RC and RS */
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* temporary fixed-point registers
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* used to emulate 64 bits target on 32 bits hosts
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*/
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target_ulong t0, t1;
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#endif
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/* Those resources are used only in Qemu core */
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CPU_COMMON
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uint32_t hflags;
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int error_code;
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uint32_t features;
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uint32_t amask;
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int implver;
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pal_handler_t *pal_handler;
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};
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#define cpu_init cpu_alpha_init
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#define cpu_exec cpu_alpha_exec
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#define cpu_gen_code cpu_alpha_gen_code
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#define cpu_signal_handler cpu_alpha_signal_handler
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _executive
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#define MMU_MODE2_SUFFIX _supervisor
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#define MMU_MODE3_SUFFIX _user
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#define MMU_USER_IDX 3
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static inline int cpu_mmu_index (CPUState *env)
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{
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return (env->ps >> 3) & 3;
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}
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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{
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if (newsp)
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env->ir[30] = newsp;
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/* FIXME: Zero syscall return value. */
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}
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#endif
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#include "cpu-all.h"
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#include "exec-all.h"
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enum {
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FEATURE_ASN = 0x00000001,
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FEATURE_SPS = 0x00000002,
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FEATURE_VIRBND = 0x00000004,
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FEATURE_TBCHK = 0x00000008,
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};
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enum {
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EXCP_RESET = 0x0000,
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EXCP_MCHK = 0x0020,
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EXCP_ARITH = 0x0060,
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EXCP_HW_INTERRUPT = 0x00E0,
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EXCP_DFAULT = 0x01E0,
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EXCP_DTB_MISS_PAL = 0x09E0,
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EXCP_ITB_MISS = 0x03E0,
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EXCP_ITB_ACV = 0x07E0,
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EXCP_DTB_MISS_NATIVE = 0x08E0,
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EXCP_UNALIGN = 0x11E0,
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EXCP_OPCDEC = 0x13E0,
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EXCP_FEN = 0x17E0,
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EXCP_CALL_PAL = 0x2000,
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EXCP_CALL_PALP = 0x3000,
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EXCP_CALL_PALE = 0x4000,
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/* Pseudo exception for console */
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EXCP_CONSOLE_DISPATCH = 0x4001,
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EXCP_CONSOLE_FIXUP = 0x4002,
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};
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/* Arithmetic exception */
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enum {
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EXCP_ARITH_OVERFLOW,
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};
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enum {
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IR_V0 = 0,
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IR_T0 = 1,
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IR_T1 = 2,
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IR_T2 = 3,
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IR_T3 = 4,
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IR_T4 = 5,
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IR_T5 = 6,
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IR_T6 = 7,
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IR_T7 = 8,
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IR_S0 = 9,
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IR_S1 = 10,
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IR_S2 = 11,
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IR_S3 = 12,
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IR_S4 = 13,
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IR_S5 = 14,
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IR_S6 = 15,
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#define IR_FP IR_S6
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IR_A0 = 16,
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IR_A1 = 17,
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IR_A2 = 18,
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IR_A3 = 19,
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IR_A4 = 20,
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IR_A5 = 21,
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IR_T8 = 22,
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IR_T9 = 23,
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IR_T10 = 24,
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IR_T11 = 25,
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IR_RA = 26,
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IR_T12 = 27,
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#define IR_PV IR_T12
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IR_AT = 28,
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IR_GP = 29,
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IR_SP = 30,
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IR_ZERO = 31,
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};
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CPUAlphaState * cpu_alpha_init (const char *cpu_model);
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int cpu_alpha_exec(CPUAlphaState *s);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_alpha_signal_handler(int host_signum, void *pinfo,
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void *puc);
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int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
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int mmu_idx, int is_softmmu);
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void do_interrupt (CPUState *env);
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int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
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int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
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void pal_init (CPUState *env);
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#if !defined (CONFIG_USER_ONLY)
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void call_pal (CPUState *env);
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#else
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void call_pal (CPUState *env, int palcode);
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#endif
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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{
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env->pc = tb->pc;
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}
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = env->ps;
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}
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#endif /* !defined (__CPU_ALPHA_H__) */
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