669b498301
Re-implemented the interconnect between the Xilinx AXI ethernet and DMA controllers. A QOM interface "stream" is created, for the two stream interfaces. As per Edgars request, this is designed to be more generic than AXI-stream, so in the future we may see more clients of this interface beyond AXI stream. This is based primarily on Paolos original refactoring of the interconnect. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
85 lines
2.7 KiB
C
85 lines
2.7 KiB
C
#include "stream.h"
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#include "qemu-common.h"
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#include "net.h"
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static inline DeviceState *
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xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xlnx.xps-intc");
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qdev_prop_set_uint32(dev, "kind-of-intr", kind_of_intr);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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/* OPB Timer/Counter. */
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static inline DeviceState *
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xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int oto, int freq)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, "xlnx,xps-timer");
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qdev_prop_set_uint32(dev, "one-timer-only", oto);
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qdev_prop_set_uint32(dev, "frequency", freq);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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/* XPS Ethernet Lite MAC. */
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static inline DeviceState *
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xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
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int txpingpong, int rxpingpong)
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{
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DeviceState *dev;
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qemu_check_nic_model(nd, "xlnx.xps-ethernetlite");
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dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint32(dev, "tx-ping-pong", txpingpong);
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qdev_prop_set_uint32(dev, "rx-ping-pong", rxpingpong);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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static inline DeviceState *
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xilinx_axiethernet_create(NICInfo *nd, StreamSlave *peer,
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target_phys_addr_t base, qemu_irq irq,
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int txmem, int rxmem)
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{
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DeviceState *dev;
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qemu_check_nic_model(nd, "xlnx.axi-ethernet");
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dev = qdev_create(NULL, "xlnx.axi-ethernet");
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qdev_set_nic_properties(dev, nd);
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qdev_prop_set_uint32(dev, "rxmem", rxmem);
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qdev_prop_set_uint32(dev, "txmem", txmem);
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object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", NULL);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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static inline void
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xilinx_axiethernetdma_init(DeviceState *dev, StreamSlave *peer,
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target_phys_addr_t base, qemu_irq irq,
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qemu_irq irq2, int freqhz)
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{
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qdev_prop_set_uint32(dev, "freqhz", freqhz);
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object_property_set_link(OBJECT(dev), OBJECT(peer), "tx_dev", NULL);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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sysbus_connect_irq(sysbus_from_qdev(dev), 1, irq2);
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}
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