b6c7e42f74
In the case where we have an interrupt generated externally from inputs to bits 1 and 2 of port A and/or port B, it is necessary to expose mos6522_update_irq() so it can be called by the interrupt source. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
156 lines
4.8 KiB
C
156 lines
4.8 KiB
C
/*
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* QEMU MOS6522 VIA emulation
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2018 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MOS6522_H
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#define MOS6522_H
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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#include "hw/ide/internal.h"
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#include "hw/input/adb.h"
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/* Bits in ACR */
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#define SR_CTRL 0x1c /* Shift register control bits */
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#define SR_EXT 0x0c /* Shift on external clock */
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#define SR_OUT 0x10 /* Shift out if 1 */
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/* Bits in IFR and IER */
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#define IER_SET 0x80 /* set bits in IER */
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#define IER_CLR 0 /* clear bits in IER */
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#define CA2_INT 0x01
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#define CA1_INT 0x02
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#define SR_INT 0x04 /* Shift register full/empty */
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#define CB2_INT 0x08
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#define CB1_INT 0x10
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#define T2_INT 0x20 /* Timer 2 interrupt */
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#define T1_INT 0x40 /* Timer 1 interrupt */
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/* Bits in ACR */
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#define T1MODE 0xc0 /* Timer 1 mode */
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#define T1MODE_CONT 0x40 /* continuous interrupts */
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/* VIA registers */
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#define VIA_REG_B 0x00
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#define VIA_REG_A 0x01
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#define VIA_REG_DIRB 0x02
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#define VIA_REG_DIRA 0x03
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#define VIA_REG_T1CL 0x04
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#define VIA_REG_T1CH 0x05
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#define VIA_REG_T1LL 0x06
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#define VIA_REG_T1LH 0x07
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#define VIA_REG_T2CL 0x08
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#define VIA_REG_T2CH 0x09
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#define VIA_REG_SR 0x0a
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#define VIA_REG_ACR 0x0b
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#define VIA_REG_PCR 0x0c
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#define VIA_REG_IFR 0x0d
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#define VIA_REG_IER 0x0e
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#define VIA_REG_ANH 0x0f
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/**
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* MOS6522Timer:
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* @counter_value: counter value at load time
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*/
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typedef struct MOS6522Timer {
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int index;
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uint16_t latch;
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uint16_t counter_value;
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int64_t load_time;
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int64_t next_irq_time;
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uint64_t frequency;
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QEMUTimer *timer;
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} MOS6522Timer;
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/**
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* MOS6522State:
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* @b: B-side data
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* @a: A-side data
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* @dirb: B-side direction (1=output)
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* @dira: A-side direction (1=output)
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* @sr: Shift register
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* @acr: Auxiliary control register
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* @pcr: Peripheral control register
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* @ifr: Interrupt flag register
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* @ier: Interrupt enable register
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* @anh: A-side data, no handshake
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* @last_b: last value of B register
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* @last_acr: last value of ACR register
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*/
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typedef struct MOS6522State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mem;
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/* VIA registers */
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uint8_t b;
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uint8_t a;
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uint8_t dirb;
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uint8_t dira;
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uint8_t sr;
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uint8_t acr;
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uint8_t pcr;
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uint8_t ifr;
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uint8_t ier;
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uint8_t anh;
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MOS6522Timer timers[2];
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uint64_t frequency;
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qemu_irq irq;
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} MOS6522State;
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#define TYPE_MOS6522 "mos6522"
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#define MOS6522(obj) OBJECT_CHECK(MOS6522State, (obj), TYPE_MOS6522)
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typedef struct MOS6522DeviceClass {
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DeviceClass parent_class;
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DeviceReset parent_reset;
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void (*set_sr_int)(MOS6522State *dev);
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void (*portB_write)(MOS6522State *dev);
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void (*portA_write)(MOS6522State *dev);
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void (*update_irq)(MOS6522State *dev);
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/* These are used to influence the CUDA MacOS timebase calibration */
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uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
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uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
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uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
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uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
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} MOS6522DeviceClass;
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#define MOS6522_DEVICE_CLASS(cls) \
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OBJECT_CLASS_CHECK(MOS6522DeviceClass, (cls), TYPE_MOS6522)
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#define MOS6522_DEVICE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522)
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extern const VMStateDescription vmstate_mos6522;
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uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
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void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
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#endif /* MOS6522_H */
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