Alistair Francis 07314158f6 target/riscv: trans_rvv: Avoid assert for RV32 and e64 ... When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside tcg_gen_gvec_dup_i32(). This patch checks that condition and instead uses tcg_gen_gvec_dup_i64() is required. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028 Suggested-by: Robert Bu <robert.bu@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-06-10 09:42:12 +10:00
..
insn_trans	target/riscv: trans_rvv: Avoid assert for RV32 and e64	2022-06-10 09:42:12 +10:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h
cpu_helper.c	target/riscv: rvv: Add tail agnostic for vv instructions	2022-06-10 09:31:42 +10:00
cpu_user.h
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: Don't expose the CPU properties on names CPUs	2022-06-10 09:31:43 +10:00
cpu.h	target/riscv: rvv: Add tail agnostic for vv instructions	2022-06-10 09:31:42 +10:00
crypto_helper.c
csr.c	target/riscv: Fix csr number based privilege checking	2022-05-24 10:38:50 +10:00
debug.c	target/riscv/debug.c: keep experimental rv128 support working	2022-06-10 09:31:42 +10:00
debug.h
fpu_helper.c
gdbstub.c
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h	target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions	2022-06-10 09:31:42 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c
machine.c
meson.build
monitor.c
op_helper.c
pmp.c
pmp.h
sbi_ecall_interface.h
trace-events
trace.h
translate.c	target/riscv: rvv: Add tail agnostic for vector load / store instructions	2022-06-10 09:31:42 +10:00
vector_helper.c	target/riscv: rvv: Add tail agnostic for vector permutation instructions	2022-06-10 09:31:42 +10:00
XVentanaCondOps.decode