Yongbok Kim d4f4f0d5d9 target-mips: fix to clear MSACSR.Cause
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-07-15 14:07:17 +01:00
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2015-07-09 17:56:56 +01:00
2015-06-23 17:46:20 +01:00

Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

- QEMU team
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