d4a2dc675b
Add new helpers exception_with_syndrome (for generating an exception with syndrome information) and exception_uncategorized (for generating an exception with "Unknown or Uncategorized Reason", which have a syndrome register value of zero), and use them to generate the correct syndrome information for exceptions which are raised directly from generated code. This patch includes moving the A32/T32 gen_exception_insn functions further up in the source file; they will be needed for "VFP/Neon disabled" exception generation later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
#ifndef TARGET_ARM_TRANSLATE_H
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#define TARGET_ARM_TRANSLATE_H
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/* internal defines */
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typedef struct DisasContext {
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target_ulong pc;
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uint32_t insn;
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int is_jmp;
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/* Nonzero if this instruction has been conditionally skipped. */
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int condjmp;
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/* The label that will be jumped to when the instruction is skipped. */
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int condlabel;
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/* Thumb-2 conditional execution bits. */
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int condexec_mask;
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int condexec_cond;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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int thumb;
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int bswap_code;
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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int vfp_enabled;
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int vec_len;
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int vec_stride;
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/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
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* so that top level loop can generate correct syndrome information.
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*/
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uint32_t svc_imm;
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int aarch64;
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int current_pl;
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GHashTable *cp_regs;
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uint64_t features; /* CPU features bits */
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#define TMP_A64_MAX 16
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int tmp_a64_count;
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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} DisasContext;
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extern TCGv_ptr cpu_env;
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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return (dc->features & (1ULL << feature)) != 0;
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}
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/* target-specific extra values for is_jmp */
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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#define DISAS_WFI 4
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#define DISAS_SWI 5
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/* For instructions which unconditionally cause an exception we can skip
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* emitting unreachable code at the end of the TB in the A64 decoder
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*/
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#define DISAS_EXC 6
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/* WFE */
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#define DISAS_WFE 7
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#ifdef TARGET_AARCH64
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void a64_translate_init(void);
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void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc);
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void gen_a64_set_pc_im(uint64_t val);
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#else
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static inline void a64_translate_init(void)
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{
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}
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static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
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TranslationBlock *tb,
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bool search_pc)
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{
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}
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static inline void gen_a64_set_pc_im(uint64_t val)
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{
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}
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#endif
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void arm_gen_test_cc(int cc, int label);
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#endif /* TARGET_ARM_TRANSLATE_H */
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