Lara Lazier d499f196fe target/i386: Added consistency checks for EFER ... EFER.SVME has to be set, and EFER reserved bits must be zero. In addition the combinations * EFER.LMA or EFER.LME is non-zero and the processor does not support LM * non-zero EFER.LME and CR0.PG and zero CR4.PAE * non-zero EFER.LME and CR0.PG and zero CR0.PE * non-zero EFER.LME, CR0.PG, CR4.PAE, CS.L and CS.D are all invalid. (AMD64 Architecture Programmer's Manual, V2, 15.5) Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210721152651.14683-3-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2021-07-22 14:44:47 +02:00
..
sysemu	target/i386: Added consistency checks for EFER	2021-07-22 14:44:47 +02:00
user	target/i386: Remove user-only i/o stubs	2021-05-19 12:17:23 -05:00
bpt_helper.c	target/i386: fix exceptions for MOV to DR	2021-07-09 18:21:34 +02:00
cc_helper_template.h
cc_helper.c
excp_helper.c	target/i386: Mark some helpers as noreturn	2021-05-19 12:17:11 -05:00
fpu_helper.c	target/i386: Correct implementation for FCS, FIP, FDS and FDP	2021-07-13 08:13:19 -07:00
helper-tcg.h	target/i386: Move invlpg, hlt, monitor, mwait to sysemu	2021-05-19 12:17:11 -05:00
int_helper.c
mem_helper.c	exec: Use cpu_untagged_addr in g2h; split out g2h_untagged	2021-02-16 11:04:53 +00:00
meson.build	i386: split svm_helper into sysemu and stub-only user	2021-05-10 15:41:51 -04:00
misc_helper.c	target/i386: Move invlpg, hlt, monitor, mwait to sysemu	2021-05-19 12:17:11 -05:00
mpx_helper.c
seg_helper.c	target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa	2021-06-04 13:47:08 +02:00
seg_helper.h	i386: split seg_helper into user-only and sysemu parts	2021-05-10 15:41:52 -04:00
tcg-cpu.c	target/i386: Populate x86_ext_save_areas offsets using cpuid where possible	2021-07-06 08:33:48 +02:00
tcg-cpu.h	target/i386: Move X86XSaveArea into TCG	2021-07-06 08:33:51 +02:00
tcg-stub.c
translate.c	target/i386: Correct implementation for FCS, FIP, FDS and FDP	2021-07-13 08:13:19 -07:00