Jonathan Cameron 3a95f57211 hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge. ... This CXL component isn't allowed to have a RAS capability. Whilst this should be harmless as software is not expected to look here, good to clean it up. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240215155206.2736-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-03-12 17:56:55 -04:00
..
cxl_downstream.c	hw/cxl: Standardize all references on CXL r3.1 and minor updates	2024-02-14 06:09:33 -05:00
cxl_root_port.c	hw/cxl: Standardize all references on CXL r3.1 and minor updates	2024-02-14 06:09:33 -05:00
cxl_upstream.c	hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()	2024-03-09 18:56:37 +03:00
gen_pcie_root_port.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00
i82801b11.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00
ioh3420.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00
Kconfig	hw/pci-bridge: make building pcie-to-pci bridge configurable	2023-05-19 10:30:46 -04:00
meson.build	meson: remove CONFIG_ALL	2023-12-31 09:11:28 +01:00
pci_bridge_dev.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00
pci_expander_bridge_stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
pci_expander_bridge.c	hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.	2024-03-12 17:56:55 -04:00
pcie_pci_bridge.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00
pcie_root_port.c	pci: drop redundant PCIDeviceClass::is_bridge field	2022-12-21 07:32:24 -05:00
simba.c	pci: drop redundant PCIDeviceClass::is_bridge field	2022-12-21 07:32:24 -05:00
xio3130_downstream.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00
xio3130_upstream.c	hw/pci-bridge: Constify VMState	2023-12-30 07:38:06 +11:00