205ccfd7a5
When building QEMU with DEBUG_ATI defined then running with '-device ati-vga,romfile="" -d unimp,guest_errors -trace ati\*' we get: ati_mm_write 4 0x16c0 DP_CNTL <- 0x1 ati_mm_write 4 0x146c DP_GUI_MASTER_CNTL <- 0x2 ati_mm_write 4 0x16c8 DP_MIX <- 0xff0000 ati_mm_write 4 0x16c4 DP_DATATYPE <- 0x2 ati_mm_write 4 0x224 CRTC_OFFSET <- 0x0 ati_mm_write 4 0x142c DST_PITCH_OFFSET <- 0xfe00000 ati_mm_write 4 0x1420 DST_Y <- 0x3fff ati_mm_write 4 0x1410 DST_HEIGHT <- 0x3fff ati_mm_write 4 0x1588 DST_WIDTH_X <- 0x3fff3fff ati_2d_blt: vram:0x7fff5fa00000 addr:0 ds:0x7fff61273800 stride:2560 bpp:32 rop:0xff ati_2d_blt: 0 0 0, 0 127 0, (0,0) -> (16383,16383) 16383x16383 > ^ ati_2d_blt: pixman_fill(dst:0x7fff5fa00000, stride:254, bpp:8, x:16383, y:16383, w:16383, h:16383, xor:0xff000000) Thread 3 "qemu-system-i38" received signal SIGSEGV, Segmentation fault. (gdb) bt #0 0x00007ffff7f62ce0 in sse2_fill.lto_priv () at /lib64/libpixman-1.so.0 #1 0x00007ffff7f09278 in pixman_fill () at /lib64/libpixman-1.so.0 #2 0x0000555557b5a9af in ati_2d_blt (s=0x631000028800) at hw/display/ati_2d.c:196 #3 0x0000555557b4b5a2 in ati_mm_write (opaque=0x631000028800, addr=5512, data=1073692671, size=4) at hw/display/ati.c:843 #4 0x0000555558b90ec4 in memory_region_write_accessor (mr=0x631000039cc0, addr=5512, ..., size=4, ...) at softmmu/memory.c:492 Commit584acf34cb("ati-vga: Fix reverse bit blts") introduced the local dst_x and dst_y which adjust the (x, y) coordinates depending on the direction in the SRCCOPY ROP3 operation, but forgot to address the same issue for the PATCOPY, BLACKNESS and WHITENESS operations, which also call pixman_fill(). Fix that now by using the adjusted coordinates in the pixman_fill call, and update the related debug printf(). Reported-by: Qiang Liu <qiangliu@zju.edu.cn> Fixes:584acf34cb("ati-vga: Fix reverse bit blts") Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Mauro Matteo Cascella <mcascell@redhat.com> Message-Id: <20210906153103.1661195-1-philmd@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
207 lines
8.3 KiB
C
207 lines
8.3 KiB
C
/*
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* QEMU ATI SVGA emulation
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* 2D engine functions
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*
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* Copyright (c) 2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "ati_int.h"
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#include "ati_regs.h"
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#include "qemu/log.h"
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#include "ui/pixel_ops.h"
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/*
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* NOTE:
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* This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
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* reinvent the wheel (unlikely to get better with a naive implementation than
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* existing libraries) and avoid (poorly) reimplementing gfx primitives.
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* That is unnecessary and would become a performance problem. Instead, try to
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* map to and reuse existing optimised facilities (e.g. pixman) wherever
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* possible.
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*/
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static int ati_bpp_from_datatype(ATIVGAState *s)
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{
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switch (s->regs.dp_datatype & 0xf) {
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case 2:
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return 8;
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case 3:
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case 4:
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return 16;
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case 5:
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return 24;
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case 6:
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return 32;
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default:
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qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
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s->regs.dp_datatype & 0xf);
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return 0;
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}
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}
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#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
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void ati_2d_blt(ATIVGAState *s)
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{
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/* FIXME it is probably more complex than this and may need to be */
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/* rewritten but for now as a start just to get some output: */
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DisplaySurface *ds = qemu_console_surface(s->vga.con);
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DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
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s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
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surface_bits_per_pixel(ds),
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(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
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unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
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s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
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unsigned dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
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int bpp = ati_bpp_from_datatype(s);
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if (!bpp) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
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return;
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}
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int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
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if (!dst_stride) {
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qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
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return;
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}
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uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
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s->regs.dst_offset : s->regs.default_offset);
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
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dst_bits += s->regs.crtc_offset & 0x07ffffff;
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dst_stride *= bpp;
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}
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uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
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if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >= end
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|| dst_bits + dst_x
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+ (dst_y + s->regs.dst_height) * dst_stride >= end) {
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
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return;
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}
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DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
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s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
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s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
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s->regs.src_x, s->regs.src_y, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height,
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(s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
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(s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
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switch (s->regs.dp_mix & GMC_ROP3_MASK) {
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case ROP3_SRCCOPY:
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{
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unsigned src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
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s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
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unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
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int src_stride = DEFAULT_CNTL ?
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s->regs.src_pitch : s->regs.default_pitch;
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if (!src_stride) {
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qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
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return;
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}
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uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
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s->regs.src_offset : s->regs.default_offset);
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
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src_bits += s->regs.crtc_offset & 0x07ffffff;
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src_stride *= bpp;
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}
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if (src_x > 0x3fff || src_y > 0x3fff || src_bits >= end
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|| src_bits + src_x
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+ (src_y + s->regs.dst_height) * src_stride >= end) {
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
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return;
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}
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src_stride /= sizeof(uint32_t);
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dst_stride /= sizeof(uint32_t);
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DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
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src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
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src_x, src_y, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height);
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if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
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s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
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pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
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src_stride, dst_stride, bpp, bpp,
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src_x, src_y, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height);
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} else {
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/* FIXME: We only really need a temporary if src and dst overlap */
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int llb = s->regs.dst_width * (bpp / 8);
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int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
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uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *
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s->regs.dst_height);
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pixman_blt((uint32_t *)src_bits, tmp,
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src_stride, tmp_stride, bpp, bpp,
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src_x, src_y, 0, 0,
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s->regs.dst_width, s->regs.dst_height);
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pixman_blt(tmp, (uint32_t *)dst_bits,
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tmp_stride, dst_stride, bpp, bpp,
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0, 0, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height);
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g_free(tmp);
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}
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if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
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dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
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s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
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memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
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s->regs.dst_offset +
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dst_y * surface_stride(ds),
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s->regs.dst_height * surface_stride(ds));
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}
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s->regs.dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
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dst_x + s->regs.dst_width : dst_x);
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s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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dst_y + s->regs.dst_height : dst_y);
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break;
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}
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case ROP3_PATCOPY:
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case ROP3_BLACKNESS:
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case ROP3_WHITENESS:
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{
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uint32_t filler = 0;
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switch (s->regs.dp_mix & GMC_ROP3_MASK) {
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case ROP3_PATCOPY:
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filler = s->regs.dp_brush_frgd_clr;
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break;
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case ROP3_BLACKNESS:
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filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],
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s->vga.palette[1], s->vga.palette[2]);
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break;
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case ROP3_WHITENESS:
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filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],
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s->vga.palette[4], s->vga.palette[5]);
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break;
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}
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dst_stride /= sizeof(uint32_t);
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DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
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dst_bits, dst_stride, bpp,
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dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height,
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filler);
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pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
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dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height,
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filler);
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if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
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dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
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s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
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memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
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s->regs.dst_offset +
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dst_y * surface_stride(ds),
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s->regs.dst_height * surface_stride(ds));
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}
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s->regs.dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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dst_y + s->regs.dst_height : dst_y);
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break;
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}
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default:
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qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
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(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
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}
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}
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