74c21bd074
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1449505425-32022-3-git-send-email-peter.maydell@linaro.org
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
|
|
* ARM gdb server stub
|
|
*
|
|
* Copyright (c) 2003-2005 Fabrice Bellard
|
|
* Copyright (c) 2013 SUSE LINUX Products GmbH
|
|
*
|
|
* This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
* License as published by the Free Software Foundation; either
|
|
* version 2 of the License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* Lesser General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
#include "qemu/osdep.h"
|
|
#include "qemu-common.h"
|
|
#include "exec/gdbstub.h"
|
|
|
|
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
|
|
whatever the target description contains. Due to a historical mishap
|
|
the FPA registers appear in between core integer regs and the CPSR.
|
|
We hack round this by giving the FPA regs zero size when talking to a
|
|
newer gdb. */
|
|
|
|
int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
if (n < 16) {
|
|
/* Core integer register. */
|
|
return gdb_get_reg32(mem_buf, env->regs[n]);
|
|
}
|
|
if (n < 24) {
|
|
/* FPA registers. */
|
|
if (gdb_has_xml) {
|
|
return 0;
|
|
}
|
|
memset(mem_buf, 0, 12);
|
|
return 12;
|
|
}
|
|
switch (n) {
|
|
case 24:
|
|
/* FPA status register. */
|
|
if (gdb_has_xml) {
|
|
return 0;
|
|
}
|
|
return gdb_get_reg32(mem_buf, 0);
|
|
case 25:
|
|
/* CPSR */
|
|
return gdb_get_reg32(mem_buf, cpsr_read(env));
|
|
}
|
|
/* Unknown register. */
|
|
return 0;
|
|
}
|
|
|
|
int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
uint32_t tmp;
|
|
|
|
tmp = ldl_p(mem_buf);
|
|
|
|
/* Mask out low bit of PC to workaround gdb bugs. This will probably
|
|
cause problems if we ever implement the Jazelle DBX extensions. */
|
|
if (n == 15) {
|
|
tmp &= ~1;
|
|
}
|
|
|
|
if (n < 16) {
|
|
/* Core integer register. */
|
|
env->regs[n] = tmp;
|
|
return 4;
|
|
}
|
|
if (n < 24) { /* 16-23 */
|
|
/* FPA registers (ignored). */
|
|
if (gdb_has_xml) {
|
|
return 0;
|
|
}
|
|
return 12;
|
|
}
|
|
switch (n) {
|
|
case 24:
|
|
/* FPA status register (ignored). */
|
|
if (gdb_has_xml) {
|
|
return 0;
|
|
}
|
|
return 4;
|
|
case 25:
|
|
/* CPSR */
|
|
cpsr_write(env, tmp, 0xffffffff);
|
|
return 4;
|
|
}
|
|
/* Unknown register. */
|
|
return 0;
|
|
}
|