Kito Cheng 620455350a

target/riscv: Fix wrong expanding for c.fswsp ...

base register is no rs1 not rs2 for fsw.

Signed-off-by: Kito Cheng <kito.cheng@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-03-26 03:17:30 -07:00

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alpha

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arm

Pull request

2019-03-25 17:01:10 +00:00

cris

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hppa

trace-events: Shorten file names in comments

2019-03-22 16:18:07 +00:00

i386

trace-events: Shorten file names in comments

2019-03-22 16:18:07 +00:00

lm32

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m68k

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microblaze

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mips

trace-events: Shorten file names in comments

2019-03-22 16:18:07 +00:00

moxie

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nios2

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openrisc

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ppc

trace-events: Shorten file names in comments

2019-03-22 16:18:07 +00:00

riscv

target/riscv: Fix wrong expanding for c.fswsp

2019-03-26 03:17:30 -07:00

s390x

trace-events: Shorten file names in comments

2019-03-22 16:18:07 +00:00

sh4

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sparc

trace-events: Shorten file names in comments

2019-03-22 16:18:07 +00:00

tilegx

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tricore

tricore: fixed RCR_CADDN instruction

2019-03-08 10:00:59 +01:00

unicore32

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xtensa

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