qemu/target
Daniel Henrique Barboza d379c748a3 target/riscv: add rv64i CPU
We don't have any form of a 'bare bones' CPU. rv64, our default CPUs,
comes with a lot of defaults. This is fine for most regular uses but
it's not suitable when more control of what is actually loaded in the
CPU is required.

A bare-bones CPU would be annoying to deal with if not by profile
support, a way to load a multitude of extensions with a single flag.
Profile support is going to be implemented shortly, so let's add a CPU
for it.

The new 'rv64i' CPU will have only RVI loaded. It is inspired in the
profile specification that dictates, for RVA22U64 [1]:

"RVA22U64 Mandatory Base
 RV64I is the mandatory base ISA for RVA22U64"

And so it seems that RV64I is the mandatory base ISA for all profiles
listed in [1], making it an ideal CPU to use with profile support.

rv64i is a CPU of type TYPE_RISCV_BARE_CPU. It has a mix of features
from pre-existent CPUs:

- it allows extensions to be enabled, like generic CPUs;
- it will not inherit extension defaults, like vendor CPUs.

This is the minimum extension set to boot OpenSBI and buildroot using
rv64i:

./build/qemu-system-riscv64 -nographic -M virt \
    -cpu rv64i,sv39=true,g=true,c=true,s=true,u=true

Our minimal riscv,isa in this case will be:

 # cat /proc/device-tree/cpus/cpu@0/riscv,isa
rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd#

[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10 18:47:47 +10:00
..
alpha target/alpha: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
arm Replace "iothread lock" with "BQL" in comments 2024-01-08 10:45:43 -05:00
avr target/avr: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
cris target/cris: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
hexagon target/hexagon: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
hppa system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
i386 qemu/main-loop: rename qemu_cond_wait_iothread() to qemu_cond_wait_bql() 2024-01-08 10:45:43 -05:00
loongarch system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
m68k target/m68k: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
microblaze target/microblaze: Constify VMState in machine.c 2023-12-29 11:17:30 +11:00
mips system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
nios2 target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
openrisc system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
ppc qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD 2024-01-08 10:45:43 -05:00
riscv target/riscv: add rv64i CPU 2024-01-10 18:47:47 +10:00
rx target/rx: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
s390x system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
sh4 target/sh4: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
sparc system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
tricore target/tricore: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
xtensa system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() 2024-01-08 10:45:43 -05:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00