Jonathan Cameron f824f52947 hw/cxl: Fix missing write mask for HDM decoder target list registers ... Without being able to write these registers, no interleaving is possible. More refined checks of HDM register state on commit to follow. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Message-Id: <20220608130804.25795-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-06-09 19:32:49 -04:00
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cxl-component-utils.c	hw/cxl: Fix missing write mask for HDM decoder target list registers	2022-06-09 19:32:49 -04:00
cxl-device-utils.c	hw/cxl/device: Add memory device utilities	2022-05-13 06:13:36 -04:00
cxl-host-stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl-host.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl-mailbox-utils.c	hw/cxl/device: Implement get/set Label Storage Area (LSA)	2022-05-13 06:13:36 -04:00
Kconfig	hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)	2022-05-13 06:13:35 -04:00
meson.build	hw/cxl/host: Add support for CXL Fixed Memory Windows.	2022-05-13 07:57:26 -04:00