c59f781e3b
Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each register. The model caters to the IRQ style of both the AST2600 and the earlier SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC sub-device, while there is a single IRQ shared across all subdevices on the AST2400 and AST2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-6-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
48 lines
954 B
C
48 lines
954 B
C
/*
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* ASPEED LPC Controller
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*
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* Copyright (C) 2017-2018 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_LPC_H
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#define ASPEED_LPC_H
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#include "hw/sysbus.h"
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#include <stdint.h>
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#define TYPE_ASPEED_LPC "aspeed.lpc"
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#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)
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#define ASPEED_LPC_NR_REGS (0x260 >> 2)
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enum aspeed_lpc_subdevice {
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aspeed_lpc_kcs_1 = 0,
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aspeed_lpc_kcs_2,
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aspeed_lpc_kcs_3,
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aspeed_lpc_kcs_4,
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aspeed_lpc_ibt,
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};
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#define ASPEED_LPC_NR_SUBDEVS 5
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typedef struct AspeedLPCState {
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/* <private> */
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SysBusDevice parent;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS];
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uint32_t subdevice_irqs_pending;
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uint32_t regs[ASPEED_LPC_NR_REGS];
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uint32_t hicr7;
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} AspeedLPCState;
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#endif /* _ASPEED_LPC_H_ */
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