Peter Maydell 5acc270a35 target/xtensa fixes for 5.1: ... - fix access to special registers missing in the core configuration; - fix simcall opcode behavior for new hardware; - drop gen_io_end call from xtensa translator. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAl70W5oTHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRMpVD/9GLB9XOAZf1acFl4zR8RDqECn+Gm+E PH+ddhPPm2BqhOf7kMEl9MwPD+nBGhhXCINmIVWKcSH+5AAyquBPaNG3J8mJUgGG oJIuViPEZCeG9vPLdlzry/hNgxlkOBMUA5W7x6T+8bNUc/TSV88IOgUnC++djkxu ghkwyx29WyHH5HpQFaOoxTuZgkQa0gkc5z+lvWj2BMLVmv8z0kub4FdFh4bFJJP5 2VzBYPT9eDgyHg0Wp66ugtLr71haeJA5eKctqa6MO3XVYhmOfdkkogj25eXUwyz/ JVBMFWWbI60aQR95uPLYVSrfeUKiRHrVbi5ypFzc7Fws0b8wVGAQOuwocgIvYVK+ blQYYAvL1kJD57BOpsMFWtjdCZ8PICWGOjBzVat1elZIPPq7qbEzCh4JSfM1aqMh i4tBmid6fJOykGZNGGDryb+7KL+30SLofHrdxgQv5fzQxxf0tnHhzf5/ACx9lTRw ni2OnTS0P8SLFDJ6PT1Bb7dQUUvgOEnb9vdEt8KUkiNI+UA12fWrc6V8YHe2VeJN utXDyXWOKvkgktC0heb4PdDJDQ1Y3jVoixsqU17Xrk0ZOjQwsg+hKzR2EnMfJJPz c39tO9dLnx0Dx84Wumcnn8DZn70ksRMrhptmznPgWoIjj5Mwrhyrq+aT+atyGuSc XHRarOeKKuSq5w== =qFHa -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging target/xtensa fixes for 5.1: - fix access to special registers missing in the core configuration; - fix simcall opcode behavior for new hardware; - drop gen_io_end call from xtensa translator. # gpg: Signature made Thu 25 Jun 2020 09:08:58 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "jcmvbkbc@gmail.com" # gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown] # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full] # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200625-xtensa: target/xtensa: drop gen_io_end call target/xtensa: fix simcall for newer hardware target/xtensa: fetch HW version from configuration overlay target/xtensa: work around missing SR definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-06-25 21:20:45 +01:00
..
alpha	accel/tcg: Relax va restrictions on 64-bit guests	2020-05-15 15:25:16 +01:00
arm	target/arm: Check supported KVM features globally (not per vCPU)	2020-06-23 11:39:47 +01:00
cris	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
hppa	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00
i386	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	2020-06-15 22:06:04 +02:00
lm32	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
m68k	target/m68k: implement opcode fetoxm1	2020-06-02 13:59:02 +02:00
microblaze	target/microblaze: monitor: Increase the number of registers reported	2020-05-14 16:01:02 +02:00
mips	target/mips: msa: Split helpers for MULV.<B|H|W|D>	2020-06-15 20:51:04 +02:00
moxie	cpu: Use DeviceClass reset instead of a special CPUClass reset	2020-03-17 19:48:10 -04:00
nios2	x86 and machine queue for 5.0 soft freeze	2020-03-19 14:22:46 +00:00
openrisc	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00
ppc	target/ppc: Restrict PPCVirtualHypervisorClass to system-mode	2020-06-12 11:12:45 -04:00
riscv	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	2020-06-19 08:25:27 -07:00
rx	target/rx/translate: Add missing fall through comment	2020-04-07 18:45:54 -07:00
s390x	vfio-ccw: Add support for the schib region	2020-06-18 12:13:54 +02:00
sh4	gdbstub: Introduce gdb_get_float32() to get 32-bit float registers	2020-04-15 11:38:23 +01:00
sparc	target/sparc/int32_helper: Extract and use excp_name_str()	2020-06-09 09:21:10 +02:00
tilegx	cpu: Use DeviceClass reset instead of a special CPUClass reset	2020-03-17 19:48:10 -04:00
tricore	target/tricore: Implement gdbstub	2020-06-01 16:55:13 +02:00
unicore32	target/unicore32: Prefer qemu_semihosting_log_out() over curses	2020-06-09 19:58:53 +02:00
xtensa	target/xtensa fixes for 5.1:	2020-06-25 21:20:45 +01:00