Paolo Bonzini 5f37fd8e29 target-tricore: fix depositing bits from PCXI into ICR ... Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24 is always zero. The immediately preceding assignment is also wrong though. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1435147270-1040-1-git-send-email-pbonzini@redhat.com>		2015-06-29 14:02:58 +02:00
..
cpu-qom.h	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
cpu.c	target-tricore: introduce ISA v1.6.1 feature	2015-05-22 17:02:33 +02:00
cpu.h	target-tricore: introduce ISA v1.6.1 feature	2015-05-22 17:02:33 +02:00
csfr.def	target-tricore: Fix new typos	2015-01-15 10:44:13 +03:00
helper.c	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
helper.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00
Makefile.objs
op_helper.c	target-tricore: fix depositing bits from PCXI into ICR	2015-06-29 14:02:58 +02:00
translate.c	disas: Remove uses of CPU env	2015-06-22 17:40:01 +02:00
tricore-defs.h
tricore-opcodes.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00