qemu/target/riscv
Markus Armbruster b7d89466dd Clean up includes
Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes, with the changes
to the following files manually reverted:

    contrib/libvhost-user/libvhost-user-glib.h
    contrib/libvhost-user/libvhost-user.c
    contrib/libvhost-user/libvhost-user.h
    linux-user/mips64/cpu_loop.c
    linux-user/mips64/signal.c
    linux-user/sparc64/cpu_loop.c
    linux-user/sparc64/signal.c
    linux-user/x86_64/cpu_loop.c
    linux-user/x86_64/signal.c
    target/s390x/gen-features.c
    tests/migration/s390x/a-b-bios.c
    tests/test-rcu-simpleq.c
    tests/test-rcu-tailq.c

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20181204172535.2799-1-armbru@redhat.com>
Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Acked-by: Halil Pasic <pasic@linux.ibm.com>
Acked-by: Yuval Shaia <yuval.shaia@oracle.com>
Acked-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
2018-12-20 10:29:08 +01:00
..
cpu_bits.h RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu_helper.c RISC-V: Move non-ops from op_helper to cpu_helper 2018-10-17 13:02:14 -07:00
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
cpu.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu.h RISC-V: Allow setting and clearing multiple irqs 2018-10-17 13:02:09 -07:00
fpu_helper.c Clean up includes 2018-12-20 10:29:08 +01:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V: Move non-ops from op_helper to cpu_helper 2018-10-17 13:02:14 -07:00
op_helper.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
pmp.c target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 2018-10-30 11:04:28 -07:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V: Respect fences for user-only emulators 2018-11-13 15:12:15 -08:00