cf5ec6641e
F16C only consists of two instructions, which are a bit peculiar nevertheless. First, they access only the low half of an YMM or XMM register for the packed-half operand; the exact size still depends on the VEX.L flag. This is similar to the existing avx_movx flag, but not exactly because avx_movx is hardcoded to affect operand 2. To this end I added a "ph" format name; it's possible to reuse this approach for the VPMOVSX and VPMOVZX instructions, though that would also require adding two more formats for the low-quarter and low-eighth of an operand. Second, VCVTPS2PH is somewhat weird because it *stores* the result of the instruction into memory rather than loading it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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.. | ||
sysemu | ||
user | ||
bpt_helper.c | ||
cc_helper_template.h | ||
cc_helper.c | ||
decode-new.c.inc | ||
decode-new.h | ||
emit.c.inc | ||
excp_helper.c | ||
fpu_helper.c | ||
helper-tcg.h | ||
int_helper.c | ||
mem_helper.c | ||
meson.build | ||
misc_helper.c | ||
mpx_helper.c | ||
seg_helper.c | ||
seg_helper.h | ||
tcg-cpu.c | ||
tcg-cpu.h | ||
tcg-stub.c | ||
translate.c |