4e41d2f583
In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
92 lines
3.2 KiB
C
92 lines
3.2 KiB
C
/*
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* QEMU Xtensa CPU
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*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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/* CPUClass::reset() */
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static void xtensa_cpu_reset(CPUState *s)
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{
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XtensaCPU *cpu = XTENSA_CPU(s);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
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CPUXtensaState *env = &cpu->env;
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xcc->parent_reset(s);
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env->exception_taken = 0;
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env->pc = env->config->exception_vector[EXC_RESET];
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env->sregs[LITBASE] &= ~1;
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env->sregs[PS] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
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env->sregs[VECBASE] = env->config->vecbase;
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env->sregs[IBREAKENABLE] = 0;
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env->sregs[CACHEATTR] = 0x22222222;
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env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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env->pending_irq_level = 0;
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reset_mmu(env);
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}
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static void xtensa_cpu_initfn(Object *obj)
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{
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XtensaCPU *cpu = XTENSA_CPU(obj);
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CPUXtensaState *env = &cpu->env;
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cpu_exec_init(env);
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}
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static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
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xcc->parent_reset = cc->reset;
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cc->reset = xtensa_cpu_reset;
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}
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static const TypeInfo xtensa_cpu_type_info = {
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.name = TYPE_XTENSA_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(XtensaCPU),
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.instance_init = xtensa_cpu_initfn,
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.abstract = false,
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.class_size = sizeof(XtensaCPUClass),
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.class_init = xtensa_cpu_class_init,
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};
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static void xtensa_cpu_register_types(void)
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{
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type_register_static(&xtensa_cpu_type_info);
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}
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type_init(xtensa_cpu_register_types)
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