qemu/target/hppa
Sven Schnelle 32dc75698c target/hppa: exit TB if either Data or Instruction TLB changes
The current code assumes that we don't need to exit the TB
if a Data Cache Flush or Insert has happend. However, as we
have a shared Data/Instruction TLB, a Data cache flush also
flushes Instruction TLB entries, and a Data cache TLB insert
might also evict a Instruction TLB entry.

So exit the TB in all cases if Instruction translation is enabled.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190311191602.25796-11-svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12 09:13:43 -07:00
..
cpu-qom.h target-hppa: Add framework and enable compilation 2017-01-23 09:52:40 -08:00
cpu.c fpu/softfloat: Specialize on snan_bit_is_one 2018-05-17 15:27:15 -07:00
cpu.h target/hppa: add TLB protection id check 2019-03-12 09:13:43 -07:00
gdbstub.c target/hppa: add TLB protection id check 2019-03-12 09:13:43 -07:00
helper.c target/hppa: add TLB protection id check 2019-03-12 09:13:43 -07:00
helper.h target/hppa: add TLB protection id check 2019-03-12 09:13:43 -07:00
insns.decode target/hppa: ignore DIAG opcode 2019-03-12 09:13:43 -07:00
int_helper.c target: Do not include "exec/exec-all.h" if it is not necessary 2018-06-01 14:15:10 +02:00
machine.c vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
Makefile.objs target/hppa: Begin using scripts/decodetree.py 2019-02-12 08:48:27 -08:00
mem_helper.c target/hppa: add TLB protection id check 2019-03-12 09:13:43 -07:00
op_helper.c target/hppa: remove PSW I/R/Q bit check 2019-03-12 09:13:43 -07:00
trace-events target/hppa: add TLB trace events 2019-03-12 09:13:43 -07:00
translate.c target/hppa: exit TB if either Data or Instruction TLB changes 2019-03-12 09:13:43 -07:00