26ea091859
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2770 c046a42c-6fe2-441c-8c8c-71466251a162
884 lines
28 KiB
C
884 lines
28 KiB
C
/*
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* QEMU Malta board support
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*
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* Copyright (c) 2006 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin"
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#else
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#define BIOS_FILENAME "mipsel_bios.bin"
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#endif
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#ifdef TARGET_MIPS64
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
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#else
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#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
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#endif
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#define ENVP_ADDR (int32_t)0x80002000
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
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#define ENVP_NB_ENTRIES 16
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#define ENVP_ENTRY_SIZE 256
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extern FILE *logfile;
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typedef struct {
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uint32_t leds;
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uint32_t brk;
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uint32_t gpout;
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uint32_t i2cin;
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uint32_t i2coe;
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uint32_t i2cout;
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uint32_t i2csel;
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CharDriverState *display;
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char display_text[9];
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SerialState *uart;
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} MaltaFPGAState;
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static PITState *pit;
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/* Malta FPGA */
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static void malta_fpga_update_display(void *opaque)
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{
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char leds_text[9];
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int i;
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MaltaFPGAState *s = opaque;
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for (i = 7 ; i >= 0 ; i--) {
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if (s->leds & (1 << i))
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leds_text[i] = '#';
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else
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leds_text[i] = ' ';
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}
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leds_text[8] = '\0';
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qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
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qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
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}
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/*
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* EEPROM 24C01 / 24C02 emulation.
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*
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* Emulation for serial EEPROMs:
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* 24C01 - 1024 bit (128 x 8)
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* 24C02 - 2048 bit (256 x 8)
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*
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* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
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*/
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//~ #define DEBUG
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#if defined(DEBUG)
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# define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
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#else
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# define logout(fmt, args...) ((void)0)
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#endif
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struct _eeprom24c0x_t {
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uint8_t tick;
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uint8_t address;
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uint8_t command;
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uint8_t ack;
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uint8_t scl;
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uint8_t sda;
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uint8_t data;
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//~ uint16_t size;
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uint8_t contents[256];
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};
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typedef struct _eeprom24c0x_t eeprom24c0x_t;
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static eeprom24c0x_t eeprom = {
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contents: {
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/* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
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/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
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/* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
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/* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
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/* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
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/* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
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/* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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/* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
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},
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};
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static uint8_t eeprom24c0x_read()
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{
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logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
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eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
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return eeprom.sda;
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}
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static void eeprom24c0x_write(int scl, int sda)
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{
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if (eeprom.scl && scl && (eeprom.sda != sda)) {
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logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
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eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
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if (!sda) {
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eeprom.tick = 1;
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eeprom.command = 0;
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}
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} else if (eeprom.tick == 0 && !eeprom.ack) {
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/* Waiting for start. */
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logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
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eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
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} else if (!eeprom.scl && scl) {
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logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
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eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
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if (eeprom.ack) {
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logout("\ti2c ack bit = 0\n");
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sda = 0;
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eeprom.ack = 0;
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} else if (eeprom.sda == sda) {
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uint8_t bit = (sda != 0);
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logout("\ti2c bit = %d\n", bit);
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if (eeprom.tick < 9) {
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eeprom.command <<= 1;
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eeprom.command += bit;
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eeprom.tick++;
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if (eeprom.tick == 9) {
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logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
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eeprom.ack = 1;
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}
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} else if (eeprom.tick < 17) {
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if (eeprom.command & 1) {
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sda = ((eeprom.data & 0x80) != 0);
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}
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eeprom.address <<= 1;
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eeprom.address += bit;
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eeprom.tick++;
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eeprom.data <<= 1;
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if (eeprom.tick == 17) {
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eeprom.data = eeprom.contents[eeprom.address];
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logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
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eeprom.ack = 1;
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eeprom.tick = 0;
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}
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} else if (eeprom.tick >= 17) {
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sda = 0;
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}
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} else {
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logout("\tsda changed with raising scl\n");
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}
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} else {
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logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
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}
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eeprom.scl = scl;
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eeprom.sda = sda;
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}
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static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
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{
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MaltaFPGAState *s = opaque;
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uint32_t val = 0;
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uint32_t saddr;
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200:
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val = 0x00000000; /* All switches closed */
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break;
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/* STATUS Register */
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case 0x00208:
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#ifdef TARGET_WORDS_BIGENDIAN
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val = 0x00000012;
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#else
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val = 0x00000010;
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#endif
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break;
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/* JMPRS Register */
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case 0x00210:
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val = 0x00;
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break;
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/* LEDBAR Register */
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case 0x00408:
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val = s->leds;
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break;
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/* BRKRES Register */
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case 0x00508:
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val = s->brk;
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break;
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/* UART Registers */
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case 0x00900:
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case 0x00908:
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case 0x00910:
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case 0x00918:
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case 0x00920:
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case 0x00928:
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case 0x00930:
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case 0x00938:
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val = serial_mm_readb(s->uart, addr);
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break;
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/* GPOUT Register */
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case 0x00a00:
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val = s->gpout;
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break;
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/* XXX: implement a real I2C controller */
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/* GPINP Register */
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case 0x00a08:
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/* IN = OUT until a real I2C control is implemented */
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if (s->i2csel)
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val = s->i2cout;
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else
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val = 0x00;
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break;
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/* I2CINP Register */
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case 0x00b00:
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val = ((s->i2cin & ~1) | eeprom24c0x_read());
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break;
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/* I2COE Register */
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case 0x00b08:
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val = s->i2coe;
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break;
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/* I2COUT Register */
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case 0x00b10:
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val = s->i2cout;
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break;
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/* I2CSEL Register */
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case 0x00b18:
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val = s->i2csel;
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break;
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default:
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#if 0
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printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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}
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return val;
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}
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static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MaltaFPGAState *s = opaque;
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uint32_t saddr;
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200:
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break;
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/* JMPRS Register */
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case 0x00210:
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break;
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/* LEDBAR Register */
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/* XXX: implement a 8-LED array */
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case 0x00408:
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s->leds = val & 0xff;
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break;
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/* ASCIIWORD Register */
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case 0x00410:
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snprintf(s->display_text, 9, "%08X", val);
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malta_fpga_update_display(s);
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break;
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/* ASCIIPOS0 to ASCIIPOS7 Registers */
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case 0x00418:
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case 0x00420:
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case 0x00428:
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case 0x00430:
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case 0x00438:
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case 0x00440:
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case 0x00448:
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case 0x00450:
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s->display_text[(saddr - 0x00418) >> 3] = (char) val;
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malta_fpga_update_display(s);
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break;
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/* SOFTRES Register */
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case 0x00500:
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if (val == 0x42)
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qemu_system_reset_request ();
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break;
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/* BRKRES Register */
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case 0x00508:
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s->brk = val & 0xff;
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break;
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/* UART Registers */
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case 0x00900:
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case 0x00908:
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case 0x00910:
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case 0x00918:
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case 0x00920:
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case 0x00928:
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case 0x00930:
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case 0x00938:
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serial_mm_writeb(s->uart, addr, val);
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break;
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/* GPOUT Register */
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case 0x00a00:
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s->gpout = val & 0xff;
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break;
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/* I2COE Register */
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case 0x00b08:
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s->i2coe = val & 0x03;
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break;
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/* I2COUT Register */
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case 0x00b10:
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eeprom24c0x_write(val & 0x02, val & 0x01);
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s->i2cout = val;
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break;
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/* I2CSEL Register */
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case 0x00b18:
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s->i2csel = val & 0x01;
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break;
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default:
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#if 0
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printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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}
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}
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static CPUReadMemoryFunc *malta_fpga_read[] = {
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malta_fpga_readl,
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malta_fpga_readl,
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malta_fpga_readl
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};
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static CPUWriteMemoryFunc *malta_fpga_write[] = {
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malta_fpga_writel,
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malta_fpga_writel,
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malta_fpga_writel
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};
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void malta_fpga_reset(void *opaque)
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{
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MaltaFPGAState *s = opaque;
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s->leds = 0x00;
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s->brk = 0x0a;
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s->gpout = 0x00;
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s->i2cin = 0x3;
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s->i2coe = 0x0;
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s->i2cout = 0x3;
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s->i2csel = 0x1;
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s->display_text[8] = '\0';
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snprintf(s->display_text, 9, " ");
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malta_fpga_update_display(s);
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}
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MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
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{
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MaltaFPGAState *s;
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CharDriverState *uart_chr;
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int malta;
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s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
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malta = cpu_register_io_memory(0, malta_fpga_read,
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malta_fpga_write, s);
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cpu_register_physical_memory(base, 0x100000, malta);
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s->display = qemu_chr_open("vc");
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qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "\n");
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qemu_chr_printf(s->display, "Malta ASCII\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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uart_chr = qemu_chr_open("vc");
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qemu_chr_printf(uart_chr, "CBUS UART\r\n");
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s->uart = serial_mm_init(base, 3, env->irq[2], uart_chr, 0);
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malta_fpga_reset(s);
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qemu_register_reset(malta_fpga_reset, s);
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return s;
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}
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/* Audio support */
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#ifdef HAS_AUDIO
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static void audio_init (PCIBus *pci_bus)
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{
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struct soundhw *c;
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int audio_enabled = 0;
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for (c = soundhw; !audio_enabled && c->name; ++c) {
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audio_enabled = c->enabled;
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}
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if (audio_enabled) {
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AudioState *s;
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s = AUD_init ();
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if (s) {
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for (c = soundhw; c->name; ++c) {
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if (c->enabled) {
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if (c->isa) {
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fprintf(stderr, "qemu: Unsupported Sound Card: %s\n", c->name);
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exit(1);
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}
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else {
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if (pci_bus) {
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c->init.init_pci (pci_bus, s);
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}
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}
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}
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}
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}
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}
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}
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#endif
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/* Network support */
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static void network_init (PCIBus *pci_bus)
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{
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int i;
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NICInfo *nd;
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for(i = 0; i < nb_nics; i++) {
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nd = &nd_table[i];
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|
if (!nd->model) {
|
|
nd->model = "pcnet";
|
|
}
|
|
if (i == 0 && strcmp(nd->model, "pcnet") == 0) {
|
|
/* The malta board has a PCNet card using PCI SLOT 11 */
|
|
pci_nic_init(pci_bus, nd, 88);
|
|
} else {
|
|
pci_nic_init(pci_bus, nd, -1);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* ROM and pseudo bootloader
|
|
|
|
The following code implements a very very simple bootloader. It first
|
|
loads the registers a0 to a3 to the values expected by the OS, and
|
|
then jump at the kernel address.
|
|
|
|
The bootloader should pass the locations of the kernel arguments and
|
|
environment variables tables. Those tables contain the 32-bit address
|
|
of NULL terminated strings. The environment variables table should be
|
|
terminated by a NULL address.
|
|
|
|
For a simpler implementation, the number of kernel arguments is fixed
|
|
to two (the name of the kernel and the command line), and the two
|
|
tables are actually the same one.
|
|
|
|
The registers a0 to a3 should contain the following values:
|
|
a0 - number of kernel arguments
|
|
a1 - 32-bit address of the kernel arguments table
|
|
a2 - 32-bit address of the environment variables table
|
|
a3 - RAM size in bytes
|
|
*/
|
|
|
|
static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry)
|
|
{
|
|
uint32_t *p;
|
|
|
|
/* Small bootloader */
|
|
p = (uint32_t *) (phys_ram_base + bios_offset);
|
|
stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
|
|
/* YAMON service vector */
|
|
stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
|
|
stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
|
|
|
|
|
|
/* Second part of the bootloader */
|
|
p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
|
|
stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
|
|
stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
|
|
stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, a0, low(ENVP_ADDR) */
|
|
stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
|
|
stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
|
|
stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
|
|
stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
|
|
stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3, high(env->ram_size) */
|
|
stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
|
|
|
|
/* Load BAR registers as done by YAMON */
|
|
stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
|
|
#else
|
|
stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
|
|
#endif
|
|
stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
|
|
#else
|
|
stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
|
|
#endif
|
|
stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
|
|
#else
|
|
stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
|
|
#endif
|
|
stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
|
|
#else
|
|
stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
|
|
#endif
|
|
stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
|
|
#else
|
|
stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
|
|
#endif
|
|
stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
|
|
#else
|
|
stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
|
|
#endif
|
|
stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
|
|
|
|
/* Jump to kernel code */
|
|
stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
|
|
stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
|
|
stl_raw(p++, 0x03e00008); /* jr ra */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
|
|
/* YAMON subroutines */
|
|
p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
|
|
stl_raw(p++, 0x03e00008); /* jr ra */
|
|
stl_raw(p++, 0x24020000); /* li v0,0 */
|
|
/* 808 YAMON print */
|
|
stl_raw(p++, 0x03e06821); /* move t5,ra */
|
|
stl_raw(p++, 0x00805821); /* move t3,a0 */
|
|
stl_raw(p++, 0x00a05021); /* move t2,a1 */
|
|
stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
|
|
stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
|
|
stl_raw(p++, 0x10800005); /* beqz a0,834 */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x0ff0021c); /* jal 870 */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x08000205); /* j 814 */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x01a00008); /* jr t5 */
|
|
stl_raw(p++, 0x01602021); /* move a0,t3 */
|
|
/* 0x83c YAMON print_count */
|
|
stl_raw(p++, 0x03e06821); /* move t5,ra */
|
|
stl_raw(p++, 0x00805821); /* move t3,a0 */
|
|
stl_raw(p++, 0x00a05021); /* move t2,a1 */
|
|
stl_raw(p++, 0x00c06021); /* move t4,a2 */
|
|
stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
|
|
stl_raw(p++, 0x0ff0021c); /* jal 870 */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
|
|
stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
|
|
stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x01a00008); /* jr t5 */
|
|
stl_raw(p++, 0x01602021); /* move a0,t3 */
|
|
/* 0x870 */
|
|
stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
|
|
stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
|
|
stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
|
|
stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
|
|
stl_raw(p++, 0x00000000); /* nop */
|
|
stl_raw(p++, 0x03e00008); /* jr ra */
|
|
stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
|
|
|
|
}
|
|
|
|
static void prom_set(int index, const char *string, ...)
|
|
{
|
|
va_list ap;
|
|
int32_t *p;
|
|
int32_t table_addr;
|
|
char *s;
|
|
|
|
if (index >= ENVP_NB_ENTRIES)
|
|
return;
|
|
|
|
p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
|
|
p += index;
|
|
|
|
if (string == NULL) {
|
|
stl_raw(p, 0);
|
|
return;
|
|
}
|
|
|
|
table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
|
|
s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
|
|
|
|
stl_raw(p, table_addr);
|
|
|
|
va_start(ap, string);
|
|
vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
|
|
va_end(ap);
|
|
}
|
|
|
|
/* Kernel */
|
|
static int64_t load_kernel (CPUState *env)
|
|
{
|
|
int64_t kernel_entry, kernel_low, kernel_high;
|
|
int index = 0;
|
|
long initrd_size;
|
|
ram_addr_t initrd_offset;
|
|
|
|
if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND,
|
|
&kernel_entry, &kernel_low, &kernel_high) < 0) {
|
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
env->kernel_filename);
|
|
exit(1);
|
|
}
|
|
|
|
/* load initrd */
|
|
initrd_size = 0;
|
|
initrd_offset = 0;
|
|
if (env->initrd_filename) {
|
|
initrd_size = get_image_size (env->initrd_filename);
|
|
if (initrd_size > 0) {
|
|
initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
|
|
if (initrd_offset + initrd_size > env->ram_size) {
|
|
fprintf(stderr,
|
|
"qemu: memory too small for initial ram disk '%s'\n",
|
|
env->initrd_filename);
|
|
exit(1);
|
|
}
|
|
initrd_size = load_image(env->initrd_filename,
|
|
phys_ram_base + initrd_offset);
|
|
}
|
|
if (initrd_size == (target_ulong) -1) {
|
|
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
|
env->initrd_filename);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Store command line. */
|
|
prom_set(index++, env->kernel_filename);
|
|
if (initrd_size > 0)
|
|
prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
|
|
PHYS_TO_VIRT(initrd_offset), initrd_size,
|
|
env->kernel_cmdline);
|
|
else
|
|
prom_set(index++, env->kernel_cmdline);
|
|
|
|
/* Setup minimum environment variables */
|
|
prom_set(index++, "memsize");
|
|
prom_set(index++, "%i", env->ram_size);
|
|
prom_set(index++, "modetty0");
|
|
prom_set(index++, "38400n8r");
|
|
prom_set(index++, NULL);
|
|
|
|
return kernel_entry;
|
|
}
|
|
|
|
static void main_cpu_reset(void *opaque)
|
|
{
|
|
CPUState *env = opaque;
|
|
cpu_reset(env);
|
|
|
|
/* The bootload does not need to be rewritten as it is located in a
|
|
read only location. The kernel location and the arguments table
|
|
location does not change. */
|
|
if (env->kernel_filename) {
|
|
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
|
|
load_kernel (env);
|
|
}
|
|
}
|
|
|
|
static
|
|
void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
|
|
DisplayState *ds, const char **fd_filename, int snapshot,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
char buf[1024];
|
|
unsigned long bios_offset;
|
|
int64_t kernel_entry;
|
|
PCIBus *pci_bus;
|
|
CPUState *env;
|
|
RTCState *rtc_state;
|
|
/* fdctrl_t *floppy_controller; */
|
|
MaltaFPGAState *malta_fpga;
|
|
int ret;
|
|
mips_def_t *def;
|
|
qemu_irq *i8259;
|
|
|
|
/* init CPUs */
|
|
if (cpu_model == NULL) {
|
|
#ifdef TARGET_MIPS64
|
|
cpu_model = "R4000";
|
|
#else
|
|
cpu_model = "24Kf";
|
|
#endif
|
|
}
|
|
if (mips_find_by_name(cpu_model, &def) != 0)
|
|
def = NULL;
|
|
env = cpu_init();
|
|
cpu_mips_register(env, def);
|
|
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
|
|
qemu_register_reset(main_cpu_reset, env);
|
|
|
|
/* allocate RAM */
|
|
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
|
|
|
/* Map the bios at two physical locations, as on the real board */
|
|
bios_offset = ram_size + vga_ram_size;
|
|
cpu_register_physical_memory(0x1e000000LL,
|
|
BIOS_SIZE, bios_offset | IO_MEM_ROM);
|
|
cpu_register_physical_memory(0x1fc00000LL,
|
|
BIOS_SIZE, bios_offset | IO_MEM_ROM);
|
|
|
|
/* Load a BIOS image except if a kernel image has been specified. In
|
|
the later case, just write a small bootloader to the flash
|
|
location. */
|
|
if (kernel_filename) {
|
|
env->ram_size = ram_size;
|
|
env->kernel_filename = kernel_filename;
|
|
env->kernel_cmdline = kernel_cmdline;
|
|
env->initrd_filename = initrd_filename;
|
|
kernel_entry = load_kernel(env);
|
|
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
|
|
write_bootloader(env, bios_offset, kernel_entry);
|
|
} else {
|
|
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
|
|
ret = load_image(buf, phys_ram_base + bios_offset);
|
|
if (ret < 0 || ret > BIOS_SIZE) {
|
|
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
|
buf);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Board ID = 0x420 (Malta Board with CoreLV)
|
|
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
|
|
map to the board ID. */
|
|
stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
|
|
|
|
/* Init internal devices */
|
|
cpu_mips_irq_init_cpu(env);
|
|
cpu_mips_clock_init(env);
|
|
cpu_mips_irqctrl_init();
|
|
|
|
/* FPGA */
|
|
malta_fpga = malta_fpga_init(0x1f000000LL, env);
|
|
|
|
/* Interrupt controller */
|
|
/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
|
|
i8259 = i8259_init(env->irq[2]);
|
|
|
|
/* Northbridge */
|
|
pci_bus = pci_gt64120_init(i8259);
|
|
|
|
/* Southbridge */
|
|
piix4_init(pci_bus, 80);
|
|
pci_piix3_ide_init(pci_bus, bs_table, 81, i8259);
|
|
usb_uhci_init(pci_bus, 82);
|
|
piix4_pm_init(pci_bus, 83);
|
|
pit = pit_init(0x40, i8259[0]);
|
|
DMA_init(0);
|
|
|
|
/* Super I/O */
|
|
i8042_init(i8259[1], i8259[12], 0x60);
|
|
rtc_state = rtc_init(0x70, i8259[8]);
|
|
if (serial_hds[0])
|
|
serial_init(0x3f8, i8259[4], serial_hds[0]);
|
|
if (serial_hds[1])
|
|
serial_init(0x2f8, i8259[3], serial_hds[1]);
|
|
if (parallel_hds[0])
|
|
parallel_init(0x378, i8259[7], parallel_hds[0]);
|
|
/* XXX: The floppy controller does not work correctly, something is
|
|
probably wrong.
|
|
floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); */
|
|
|
|
/* Sound card */
|
|
#ifdef HAS_AUDIO
|
|
audio_init(pci_bus);
|
|
#endif
|
|
|
|
/* Network card */
|
|
network_init(pci_bus);
|
|
|
|
/* Optional PCI video card */
|
|
pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size,
|
|
ram_size, vga_ram_size);
|
|
}
|
|
|
|
QEMUMachine mips_malta_machine = {
|
|
"malta",
|
|
"MIPS Malta Core LV",
|
|
mips_malta_init,
|
|
};
|