5aa37f488f
Complete xtensa-semi chardev console implementation: allow reading input characters from file descriptor 0 and call sys_select_one simcall on it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
446 lines
14 KiB
C
446 lines
14 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "chardev/char-fe.h"
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#include "exec/helper-proto.h"
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#include "exec/semihost.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "sysemu/sysemu.h"
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enum {
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TARGET_SYS_exit = 1,
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TARGET_SYS_read = 3,
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TARGET_SYS_write = 4,
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TARGET_SYS_open = 5,
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TARGET_SYS_close = 6,
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TARGET_SYS_lseek = 19,
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TARGET_SYS_select_one = 29,
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TARGET_SYS_argc = 1000,
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TARGET_SYS_argv_sz = 1001,
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TARGET_SYS_argv = 1002,
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TARGET_SYS_memset = 1004,
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};
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enum {
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SELECT_ONE_READ = 1,
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SELECT_ONE_WRITE = 2,
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SELECT_ONE_EXCEPT = 3,
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};
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enum {
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TARGET_EPERM = 1,
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TARGET_ENOENT = 2,
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TARGET_ESRCH = 3,
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TARGET_EINTR = 4,
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TARGET_EIO = 5,
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TARGET_ENXIO = 6,
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TARGET_E2BIG = 7,
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TARGET_ENOEXEC = 8,
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TARGET_EBADF = 9,
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TARGET_ECHILD = 10,
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TARGET_EAGAIN = 11,
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TARGET_ENOMEM = 12,
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TARGET_EACCES = 13,
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TARGET_EFAULT = 14,
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TARGET_ENOTBLK = 15,
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TARGET_EBUSY = 16,
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TARGET_EEXIST = 17,
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TARGET_EXDEV = 18,
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TARGET_ENODEV = 19,
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TARGET_ENOTDIR = 20,
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TARGET_EISDIR = 21,
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TARGET_EINVAL = 22,
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TARGET_ENFILE = 23,
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TARGET_EMFILE = 24,
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TARGET_ENOTTY = 25,
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TARGET_ETXTBSY = 26,
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TARGET_EFBIG = 27,
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TARGET_ENOSPC = 28,
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TARGET_ESPIPE = 29,
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TARGET_EROFS = 30,
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TARGET_EMLINK = 31,
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TARGET_EPIPE = 32,
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TARGET_EDOM = 33,
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TARGET_ERANGE = 34,
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TARGET_ENOSYS = 88,
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TARGET_ELOOP = 92,
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};
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static uint32_t errno_h2g(int host_errno)
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{
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static const uint32_t guest_errno[] = {
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[EPERM] = TARGET_EPERM,
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[ENOENT] = TARGET_ENOENT,
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[ESRCH] = TARGET_ESRCH,
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[EINTR] = TARGET_EINTR,
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[EIO] = TARGET_EIO,
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[ENXIO] = TARGET_ENXIO,
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[E2BIG] = TARGET_E2BIG,
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[ENOEXEC] = TARGET_ENOEXEC,
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[EBADF] = TARGET_EBADF,
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[ECHILD] = TARGET_ECHILD,
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[EAGAIN] = TARGET_EAGAIN,
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[ENOMEM] = TARGET_ENOMEM,
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[EACCES] = TARGET_EACCES,
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[EFAULT] = TARGET_EFAULT,
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#ifdef ENOTBLK
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[ENOTBLK] = TARGET_ENOTBLK,
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#endif
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[EBUSY] = TARGET_EBUSY,
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[EEXIST] = TARGET_EEXIST,
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[EXDEV] = TARGET_EXDEV,
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[ENODEV] = TARGET_ENODEV,
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[ENOTDIR] = TARGET_ENOTDIR,
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[EISDIR] = TARGET_EISDIR,
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[EINVAL] = TARGET_EINVAL,
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[ENFILE] = TARGET_ENFILE,
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[EMFILE] = TARGET_EMFILE,
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[ENOTTY] = TARGET_ENOTTY,
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#ifdef ETXTBSY
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[ETXTBSY] = TARGET_ETXTBSY,
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#endif
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[EFBIG] = TARGET_EFBIG,
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[ENOSPC] = TARGET_ENOSPC,
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[ESPIPE] = TARGET_ESPIPE,
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[EROFS] = TARGET_EROFS,
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[EMLINK] = TARGET_EMLINK,
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[EPIPE] = TARGET_EPIPE,
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[EDOM] = TARGET_EDOM,
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[ERANGE] = TARGET_ERANGE,
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[ENOSYS] = TARGET_ENOSYS,
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#ifdef ELOOP
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[ELOOP] = TARGET_ELOOP,
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#endif
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};
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if (host_errno == 0) {
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return 0;
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} else if (host_errno > 0 && host_errno < ARRAY_SIZE(guest_errno) &&
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guest_errno[host_errno]) {
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return guest_errno[host_errno];
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} else {
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return TARGET_EINVAL;
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}
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}
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typedef struct XtensaSimConsole {
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CharBackend be;
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struct {
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char buffer[16];
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size_t offset;
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} input;
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} XtensaSimConsole;
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static XtensaSimConsole *sim_console;
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static IOCanReadHandler sim_console_can_read;
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static int sim_console_can_read(void *opaque)
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{
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XtensaSimConsole *p = opaque;
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return sizeof(p->input.buffer) - p->input.offset;
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}
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static IOReadHandler sim_console_read;
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static void sim_console_read(void *opaque, const uint8_t *buf, int size)
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{
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XtensaSimConsole *p = opaque;
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size_t copy = sizeof(p->input.buffer) - p->input.offset;
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if (size < copy) {
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copy = size;
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}
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memcpy(p->input.buffer + p->input.offset, buf, copy);
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p->input.offset += copy;
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}
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void xtensa_sim_open_console(Chardev *chr)
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{
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static XtensaSimConsole console;
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qemu_chr_fe_init(&console.be, chr, &error_abort);
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qemu_chr_fe_set_handlers(&console.be,
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sim_console_can_read,
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sim_console_read,
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NULL, NULL, &console,
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NULL, true);
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sim_console = &console;
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}
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void HELPER(simcall)(CPUXtensaState *env)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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uint32_t *regs = env->regs;
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switch (regs[2]) {
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case TARGET_SYS_exit:
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qemu_log("exit(%d) simcall\n", regs[3]);
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exit(regs[3]);
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break;
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case TARGET_SYS_read:
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case TARGET_SYS_write:
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{
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bool is_write = regs[2] == TARGET_SYS_write;
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uint32_t fd = regs[3];
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uint32_t vaddr = regs[4];
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uint32_t len = regs[5];
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uint32_t len_done = 0;
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while (len > 0) {
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hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr);
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uint32_t page_left =
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TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
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uint32_t io_sz = page_left < len ? page_left : len;
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hwaddr sz = io_sz;
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void *buf = cpu_physical_memory_map(paddr, &sz, !is_write);
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uint32_t io_done;
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bool error = false;
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if (buf) {
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vaddr += io_sz;
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len -= io_sz;
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if (fd < 3 && sim_console) {
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if (is_write && (fd == 1 || fd == 2)) {
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io_done = qemu_chr_fe_write_all(&sim_console->be,
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buf, io_sz);
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regs[3] = errno_h2g(errno);
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} else if (!is_write && fd == 0) {
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if (sim_console->input.offset) {
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io_done = sim_console->input.offset;
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if (io_sz < io_done) {
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io_done = io_sz;
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}
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memcpy(buf, sim_console->input.buffer, io_done);
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memmove(sim_console->input.buffer,
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sim_console->input.buffer + io_done,
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sim_console->input.offset - io_done);
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sim_console->input.offset -= io_done;
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qemu_chr_fe_accept_input(&sim_console->be);
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} else {
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io_done = -1;
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regs[3] = TARGET_EAGAIN;
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}
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s fd %d is not supported with chardev console\n",
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is_write ?
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"writing to" : "reading from", fd);
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io_done = -1;
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regs[3] = TARGET_EBADF;
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}
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} else {
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io_done = is_write ?
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write(fd, buf, io_sz) :
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read(fd, buf, io_sz);
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regs[3] = errno_h2g(errno);
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}
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if (io_done == -1) {
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error = true;
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io_done = 0;
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}
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cpu_physical_memory_unmap(buf, sz, !is_write, io_done);
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} else {
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error = true;
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regs[3] = TARGET_EINVAL;
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break;
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}
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if (error) {
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if (!len_done) {
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len_done = -1;
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}
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break;
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}
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len_done += io_done;
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if (io_done < io_sz) {
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break;
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}
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}
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regs[2] = len_done;
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}
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break;
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case TARGET_SYS_open:
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{
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char name[1024];
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int rc;
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int i;
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for (i = 0; i < ARRAY_SIZE(name); ++i) {
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rc = cpu_memory_rw_debug(cs, regs[3] + i,
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(uint8_t *)name + i, 1, 0);
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if (rc != 0 || name[i] == 0) {
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break;
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}
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}
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if (rc == 0 && i < ARRAY_SIZE(name)) {
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regs[2] = open(name, regs[4], regs[5]);
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regs[3] = errno_h2g(errno);
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} else {
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regs[2] = -1;
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regs[3] = TARGET_EINVAL;
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}
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}
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break;
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case TARGET_SYS_close:
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if (regs[3] < 3) {
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regs[2] = regs[3] = 0;
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} else {
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regs[2] = close(regs[3]);
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regs[3] = errno_h2g(errno);
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}
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break;
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case TARGET_SYS_lseek:
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regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]);
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regs[3] = errno_h2g(errno);
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break;
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case TARGET_SYS_select_one:
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{
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uint32_t fd = regs[3];
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uint32_t rq = regs[4];
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uint32_t target_tv = regs[5];
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uint32_t target_tvv[2];
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struct timeval tv = {0};
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if (target_tv) {
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cpu_memory_rw_debug(cs, target_tv,
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(uint8_t *)target_tvv, sizeof(target_tvv), 0);
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tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
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tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
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}
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if (fd < 3 && sim_console) {
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if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
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regs[2] = 1;
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} else if (fd == 0 && rq == SELECT_ONE_READ) {
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regs[2] = sim_console->input.offset > 0;
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} else {
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regs[2] = 0;
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}
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regs[3] = 0;
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} else {
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fd_set fdset;
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FD_ZERO(&fdset);
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FD_SET(fd, &fdset);
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regs[2] = select(fd + 1,
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rq == SELECT_ONE_READ ? &fdset : NULL,
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rq == SELECT_ONE_WRITE ? &fdset : NULL,
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rq == SELECT_ONE_EXCEPT ? &fdset : NULL,
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target_tv ? &tv : NULL);
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regs[3] = errno_h2g(errno);
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}
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}
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break;
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case TARGET_SYS_argc:
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regs[2] = semihosting_get_argc();
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regs[3] = 0;
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break;
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case TARGET_SYS_argv_sz:
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{
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int argc = semihosting_get_argc();
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int sz = (argc + 1) * sizeof(uint32_t);
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int i;
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for (i = 0; i < argc; ++i) {
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sz += 1 + strlen(semihosting_get_arg(i));
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}
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regs[2] = sz;
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regs[3] = 0;
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}
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break;
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case TARGET_SYS_argv:
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{
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int argc = semihosting_get_argc();
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int str_offset = (argc + 1) * sizeof(uint32_t);
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int i;
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uint32_t argptr;
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for (i = 0; i < argc; ++i) {
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const char *str = semihosting_get_arg(i);
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int str_size = strlen(str) + 1;
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argptr = tswap32(regs[3] + str_offset);
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cpu_memory_rw_debug(cs,
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regs[3] + i * sizeof(uint32_t),
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(uint8_t *)&argptr, sizeof(argptr), 1);
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cpu_memory_rw_debug(cs,
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regs[3] + str_offset,
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(uint8_t *)str, str_size, 1);
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str_offset += str_size;
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}
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argptr = 0;
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cpu_memory_rw_debug(cs,
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regs[3] + i * sizeof(uint32_t),
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(uint8_t *)&argptr, sizeof(argptr), 1);
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regs[3] = 0;
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}
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break;
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case TARGET_SYS_memset:
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{
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uint32_t base = regs[3];
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uint32_t sz = regs[5];
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while (sz) {
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hwaddr len = sz;
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void *buf = cpu_physical_memory_map(base, &len, 1);
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if (buf && len) {
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memset(buf, regs[4], len);
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cpu_physical_memory_unmap(buf, len, 1, len);
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} else {
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len = 1;
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}
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base += len;
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sz -= len;
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}
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regs[2] = regs[3];
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regs[3] = 0;
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s(%d): not implemented\n", __func__, regs[2]);
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regs[2] = -1;
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regs[3] = TARGET_ENOSYS;
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break;
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}
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}
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