cdfef1715c
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
464 lines
17 KiB
C
464 lines
17 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXEC_ALL_H
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#define EXEC_ALL_H
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#include "qemu-common.h"
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#include "exec/tb-context.h"
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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/* Page tracking code uses ram addresses in system mode, and virtual
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addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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type. */
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#if defined(CONFIG_USER_ONLY)
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typedef abi_ulong tb_page_addr_t;
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#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
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#else
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typedef ram_addr_t tb_page_addr_t;
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#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
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#endif
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#include "qemu/log.h"
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void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
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void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
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target_ulong *data);
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void cpu_gen_init(void);
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bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
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void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
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void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
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TranslationBlock *tb_gen_code(CPUState *cpu,
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target_ulong pc, target_ulong cs_base,
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uint32_t flags,
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int cflags);
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void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
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void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
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void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
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#if !defined(CONFIG_USER_ONLY)
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void cpu_reloading_memory_map(void);
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/**
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* cpu_address_space_init:
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* @cpu: CPU to add this address space to
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* @as: address space to add
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* @asidx: integer index of this address space
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*
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* Add the specified address space to the CPU's cpu_ases list.
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* The address space added with @asidx 0 is the one used for the
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* convenience pointer cpu->as.
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* The target-specific code which registers ASes is responsible
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* for defining what semantics address space 0, 1, 2, etc have.
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*
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* Before the first call to this function, the caller must set
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* cpu->num_ases to the total number of address spaces it needs
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* to support.
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*
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* Note that with KVM only one address space is supported.
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*/
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void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx);
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#endif
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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/* cputlb.c */
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page(CPUState *cpu, target_ulong addr);
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/**
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* tlb_flush_page_all_cpus:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
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/**
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* tlb_flush_page_all_cpus_synced:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all MMU
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* indexes like tlb_flush_page_all_cpus except the source vCPUs work
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* is scheduled as safe work meaning all flushes will be complete once
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* the source vCPUs safe work is complete. This will depend on when
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* the guests translation ends the TB.
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*/
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void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
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/**
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* tlb_flush:
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* @cpu: CPU whose TLB should be flushed
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*
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* Flush the entire TLB for the specified CPU. Most CPU architectures
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* allow the implementation to drop entries from the TLB at any time
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* so this is generally safe. If more selective flushing is required
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* use one of the other functions for efficiency.
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*/
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void tlb_flush(CPUState *cpu);
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/**
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* tlb_flush_all_cpus:
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* @cpu: src CPU of the flush
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*/
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void tlb_flush_all_cpus(CPUState *src_cpu);
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/**
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* tlb_flush_all_cpus_synced:
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* @cpu: src CPU of the flush
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*
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* Like tlb_flush_all_cpus except this except the source vCPUs work is
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* scheduled as safe work meaning all flushes will be complete once
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* the source vCPUs safe work is complete. This will depend on when
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* the guests translation ends the TB.
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*/
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void tlb_flush_all_cpus_synced(CPUState *src_cpu);
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/**
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* tlb_flush_page_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified MMU
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* indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
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* vCPUs work is scheduled as safe work meaning all flushes will be
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* complete once the source vCPUs safe work is complete. This will
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* depend on when the guests translation ends the TB.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @wait: If true ensure synchronisation by exiting the cpu_loop
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from all TLBs of all CPUs, for the specified
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* MMU indexes.
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*/
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void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from all TLBs of all CPUs, for the specified
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* MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
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* vCPUs work is scheduled as safe work meaning all flushes will be
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* complete once the source vCPUs safe work is complete. This will
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* depend on when the guests translation ends the TB.
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*/
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void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_set_page_with_attrs:
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* @cpu: CPU to add this TLB entry for
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* @vaddr: virtual address of page to add entry for
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* @paddr: physical address of the page
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* @attrs: memory transaction attributes
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* @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
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* @mmu_idx: MMU index to insert TLB entry for
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* @size: size of the page in bytes
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*
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* Add an entry to this CPU's TLB (a mapping from virtual address
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* @vaddr to physical address @paddr) with the specified memory
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* transaction attributes. This is generally called by the target CPU
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* specific code after it has been called through the tlb_fill()
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* entry point and performed a successful page table walk to find
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* the physical address and attributes for the virtual address
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* which provoked the TLB miss.
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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hwaddr paddr, MemTxAttrs attrs,
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int prot, int mmu_idx, target_ulong size);
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/* tlb_set_page:
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*
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* This function is equivalent to calling tlb_set_page_with_attrs()
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* with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
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* as a convenience for CPUs which don't use memory transaction attributes.
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*/
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void tlb_set_page(CPUState *cpu, target_ulong vaddr,
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hwaddr paddr, int prot,
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int mmu_idx, target_ulong size);
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void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
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void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr);
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#else
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static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
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{
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}
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static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
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{
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}
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static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
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target_ulong addr)
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{
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}
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static inline void tlb_flush(CPUState *cpu)
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{
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}
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static inline void tlb_flush_all_cpus(CPUState *src_cpu)
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{
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}
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static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
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{
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}
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static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
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target_ulong addr, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
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target_ulong addr,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
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target_ulong addr,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
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uint16_t idxmap)
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{
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}
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static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
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{
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}
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#endif
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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/* Estimated block size for TB allocation. */
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/* ??? The following is based on a 2015 survey of x86_64 host output.
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Better would seem to be some sort of dynamically sized TB array,
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adapting to the block sizes actually being produced. */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 400
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 150
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#endif
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/*
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* Translation Cache-related fields of a TB.
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*/
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struct tb_tc {
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void *ptr; /* pointer to the translated code */
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uint8_t *search; /* pointer to search data */
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};
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struct TranslationBlock {
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint32_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t icount;
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uint32_t cflags; /* compile flags */
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#define CF_COUNT_MASK 0x7fff
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#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
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#define CF_NOCACHE 0x10000 /* To be freed after execution */
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#define CF_USE_ICOUNT 0x20000
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#define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */
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#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */
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#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */
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/* cflags' mask for hashing/comparison */
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#define CF_HASH_MASK (CF_COUNT_MASK | CF_PARALLEL)
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/* Per-vCPU dynamic tracing state used to generate this TB */
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uint32_t trace_vcpu_dstate;
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struct tb_tc tc;
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/* original tb when cflags has CF_NOCACHE */
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struct TranslationBlock *orig_tb;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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tb_page_addr_t page_addr[2];
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/* The following data are used to directly call another TB from
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* the code of this one. This can be done either by emitting direct or
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* indirect native jump instructions. These jumps are reset so that the TB
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* just continues its execution. The TB can be linked to another one by
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* setting one of the jump targets (or patching the jump instruction). Only
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* two of such jumps are supported.
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*/
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uint16_t jmp_reset_offset[2]; /* offset of original jump target */
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#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
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uintptr_t jmp_target_arg[2]; /* target address or offset */
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/* Each TB has an associated circular list of TBs jumping to this one.
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* jmp_list_first points to the first TB jumping to this one.
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* jmp_list_next is used to point to the next TB in a list.
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* Since each TB can have two jumps, it can participate in two lists.
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* jmp_list_first and jmp_list_next are 4-byte aligned pointers to a
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* TranslationBlock structure, but the two least significant bits of
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* them are used to encode which data field of the pointed TB should
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* be used to traverse the list further from that TB:
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* 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first.
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* In other words, 0/1 tells which jump is used in the pointed TB,
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* and 2 means that this is a pointer back to the target TB of this list.
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*/
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uintptr_t jmp_list_next[2];
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uintptr_t jmp_list_first;
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};
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extern bool parallel_cpus;
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/* Hide the atomic_read to make code a little easier on the eyes */
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static inline uint32_t tb_cflags(const TranslationBlock *tb)
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{
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return atomic_read(&tb->cflags);
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}
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/* current cflags for hashing/comparison */
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static inline uint32_t curr_cflags(void)
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{
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return parallel_cpus ? CF_PARALLEL : 0;
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}
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void tb_free(TranslationBlock *tb);
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void tb_flush(CPUState *cpu);
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
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target_ulong cs_base, uint32_t flags,
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uint32_t cf_mask);
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void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
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/* GETPC is the true target of the return instruction that we'll execute. */
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#if defined(CONFIG_TCG_INTERPRETER)
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extern uintptr_t tci_tb_ptr;
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# define GETPC() tci_tb_ptr
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#else
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# define GETPC() \
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((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
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#endif
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/* The true return address will often point to a host insn that is part of
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the next translated guest insn. Adjust the address backward to point to
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the middle of the call insn. Subtracting one would do the job except for
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several compressed mode architectures (arm, mips) which set the low bit
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to indicate the compressed mode; subtracting two works around that. It
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is also the case that there are no host isas that contain a call insn
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smaller than 4 bytes, so we don't worry about special-casing this. */
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#define GETPC_ADJ 2
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void tb_lock(void);
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void tb_unlock(void);
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void tb_lock_reset(void);
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#if !defined(CONFIG_USER_ONLY)
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struct MemoryRegion *iotlb_to_region(CPUState *cpu,
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hwaddr index, MemTxAttrs attrs);
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void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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#endif
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#if defined(CONFIG_USER_ONLY)
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void mmap_lock(void);
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void mmap_unlock(void);
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bool have_mmap_lock(void);
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static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
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{
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return addr;
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}
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#else
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static inline void mmap_lock(void) {}
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static inline void mmap_unlock(void) {}
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/* cputlb.c */
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tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
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void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
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/* exec.c */
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void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
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MemoryRegionSection *
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address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
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hwaddr *xlat, hwaddr *plen);
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hwaddr memory_region_section_get_iotlb(CPUState *cpu,
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MemoryRegionSection *section,
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target_ulong vaddr,
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hwaddr paddr, hwaddr xlat,
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int prot,
|
|
target_ulong *address);
|
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bool memory_region_is_unassigned(MemoryRegion *mr);
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|
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#endif
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|
|
|
/* vl.c */
|
|
extern int singlestep;
|
|
|
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#endif
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