Philippe Mathieu-Daudé cde0a41c12 target/ppc: Optimize xviexpdp() using deposit_i64() ... The t0 tcg_temp register is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-2-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2019-03-12 14:33:05 +11:00
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dfp-impl.inc.c	target/ppc: move FP and VMX registers into aligned vsr register array	2019-01-09 09:28:14 +11:00
dfp-ops.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
fp-impl.inc.c	target/ppc: introduce get_fpr() and set_fpr() helpers for FP register access	2019-01-09 09:28:13 +11:00
fp-ops.inc.c	target/ppc: add external PID support	2018-11-08 12:04:40 +11:00
spe-impl.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
spe-ops.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
vmx-impl.inc.c	target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64()	2019-03-12 14:33:04 +11:00
vmx-ops.inc.c	Changes requirement for "vsubsbs" instruction	2018-12-21 09:29:12 +11:00
vsx-impl.inc.c	target/ppc: Optimize xviexpdp() using deposit_i64()	2019-03-12 14:33:05 +11:00
vsx-ops.inc.c	target-ppc: Add xscvqpudz and xscvqpuwz instructions	2017-02-22 11:28:28 +11:00