f780e63fe7
Add documentation for the mps3-an536 board type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
89 lines
3.9 KiB
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89 lines
3.9 KiB
ReStructuredText
Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
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=========================================================================================================================================================================
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These board models use Arm M-profile or R-profile CPUs.
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The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
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bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
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FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
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Since the CPU itself and most of the devices are in the FPGA, the
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details of the board as seen by the guest depend significantly on the
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FPGA image.
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QEMU models the following FPGA images:
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FPGA images using M-profile CPUs:
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``mps2-an385``
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Cortex-M3 as documented in Arm Application Note AN385
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``mps2-an386``
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Cortex-M4 as documented in Arm Application Note AN386
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``mps2-an500``
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Cortex-M7 as documented in Arm Application Note AN500
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``mps2-an505``
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Cortex-M33 as documented in Arm Application Note AN505
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``mps2-an511``
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Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
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``mps2-an521``
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Dual Cortex-M33 as documented in Arm Application Note AN521
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``mps3-an524``
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Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524
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``mps3-an547``
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Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
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FPGA images using R-profile CPUs:
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``mps3-an536``
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Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
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Differences between QEMU and real hardware:
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- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
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block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
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if zbt_boot_ctrl is always zero)
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- AN524 remapping of low memory to either BRAM or to QSPI flash is
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unimplemented (QEMU always maps this to BRAM, ignoring the
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SCC CFG_REG0 memory-remap bit)
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- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
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visible difference is that the LAN9118 doesn't support checksum
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offloading
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- QEMU does not model the QSPI flash in MPS3 boards as real QSPI
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flash, but only as simple ROM, so attempting to rewrite the flash
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from the guest will fail
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- QEMU does not model the USB controller in MPS3 boards
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- AN536 does not support runtime control of CPU reset and halt via
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the SCC CFG_REG0 register.
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- AN536 does not support enabling or disabling the flash and ATCM
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interfaces via the SCC CFG_REG1 register.
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- AN536 does not support setting of the initial vector table
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base address via the SCC CFG_REG6 and CFG_REG7 register config,
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and does not provide a mechanism for specifying these values at
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startup, so all guest images must be built to start from TCM
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(i.e. to expect the interrupt vector base at 0 from reset).
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- AN536 defaults to only creating a single CPU; this is the equivalent
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of the way the real FPGA image usually runs with the second Cortex-R52
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held in halt via the initial SCC CFG_REG0 register setting. You can
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create the second CPU with ``-smp 2``; both CPUs will then start
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execution immediately on startup.
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Note that for the AN536 the first UART is accessible only by
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CPU0, and the second UART is accessible only by CPU1. The
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first UART accessible shared between both CPUs is the third
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UART. Guest software might therefore be built to use either
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the first UART or the third UART; if you don't see any output
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from the UART you are looking at, try one of the others.
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(Even if the AN536 machine is started with a single CPU and so
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no "CPU1-only UART", the UART numbering remains the same,
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with the third UART being the first of the shared ones.)
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Machine-specific options
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""""""""""""""""""""""""
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The following machine-specific options are supported:
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remap
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Supported for ``mps3-an524`` only.
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Set ``BRAM``/``QSPI`` to select the initial memory mapping. The
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default is ``BRAM``.
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