Yongbok Kim c870e3f52c target-mips: add CMGCRBase register ... Physical base address for the memory-mapped Coherency Manager Global Configuration Register space. The MIPS default location for the GCR_BASE address is 0x1FBF_8. This register only exists if Config3 CMGCR is set to one. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: move CMGCR enabling to a separate patch] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>		2016-03-30 09:13:59 +01:00
..
cpu-qom.h	target-mips: replace cpu_save/cpu_load with VMStateDescription	2015-03-11 14:13:57 +00:00
cpu.c	include/qemu/osdep.h: Don't include qapi/error.h	2016-03-22 22:20:15 +01:00
cpu.h	target-mips: add CMGCRBase register	2016-03-30 09:13:59 +01:00
dsp_helper.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
gdbstub.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
helper.c	log: do not unnecessarily include qom/cpu.h	2016-02-03 09:19:10 +00:00
helper.h	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
kvm_mips.h	target-mips: kvm: Add main KVM support for MIPS	2014-06-18 16:58:52 +02:00
kvm.c	mips/kvm: Support MSA in MIPS KVM guests	2016-02-26 08:59:17 +00:00
lmi_helper.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
machine.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
Makefile.objs	target-mips: add Unified Hosting Interface (UHI) support	2015-06-26 09:08:50 +01:00
mips-defs.h	target-mips: fix MIPS64R6-generic configuration	2015-07-15 14:07:10 +01:00
mips-semi.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
msa_helper.c	mips: Clean up includes	2016-01-23 14:30:04 +00:00
op_helper.c	target-mips: implement R6 multi-threading	2016-02-26 08:59:17 +00:00
TODO
translate_init.c	target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs	2016-03-23 13:36:55 +00:00
translate.c	target-mips: add CMGCRBase register	2016-03-30 09:13:59 +01:00