Andrew Jones cbbb3041fe target/arm: fix crash on pmu register access ... Fix a QEMU NULL derefence that occurs when the guest attempts to enable PMU counters with a non-v8 cpu model or a v8 cpu model which has not configured a PMU. Fixes: 4e7beb0cc0 ("target/arm: Add a timer to predict PMU counter overflow") Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190322162333.17159-2-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2019-03-25 14:16:47 +00:00
..
alpha
arm	target/arm: fix crash on pmu register access	2019-03-25 14:16:47 +00:00
cris
hppa
i386	i386: Disable OSPKE on CPU model definitions	2019-03-20 12:18:15 -03:00
lm32
m68k
microblaze
mips
moxie
nios2
openrisc
ppc
riscv	target/riscv: Remove unused struct	2019-03-19 05:14:40 -07:00
s390x
sh4
sparc
tilegx
tricore
unicore32
xtensa